Epson S1C17001 Technical Manual page 226

The UART allows receive buffer full interrupts to be generated once data has been received in the receive data
buffer. These interrupts can be used to read the receive data buffer. With default settings, a receive buffer full
interrupt occurs when the receive data buffer receives one item of data (status (2) above). This can be changed
by setting the RBFI bit (D1/UART_CTL register) to 1 so that an interrupt occurs when the receive data buffer
receives two items of data.
∗ RBFI: Receive Buffer Full Interrupt Condition Setup Bit in the UART Control (UART_CTL) Register (D1/0x4104)
Three error flags are also provided in addition to the flags previously mentioned. See Section 18.6 for detailed
information on flags and receive errors.
Sampling clock
SIN
Receive data buffer
RDRY
RD2B
RXD[7:0]
Interrupt
Blocking data transfers
After a data transfer is completed (both transmission and reception), data transfers are blocked by writing 0 to
the RXEN bit. Confirm that the TDBE flag is 1 and the TRBS and RDRY flags are both 0 before blocking data
transfer.
Setting the RXEN bit to 0 empties the transmission and receive data buffers, clearing any remaining data. The
data being transferred cannot be guaranteed if RXEN is set to 0 while data is being sent or received.
S1C17001 TECHNICAL MANUAL
data 1 data 2
S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2 S1 D0 ··· P S2
data 1 –
Rd
data 1
Receive buffer full interrupt request
S1: Start bit, S2: Stop bit, P: Parity bit, Rd: Data bits from RXD[7:0]
Figure 18.5.2: Data receiving timing chart
EPSON
data 3 data 4
data 2 data 2, 3 data 3
Rd
data 2
(RBFI = 0)
18 UART
data 5 data 6
data 3, 4
data 3
Overrun error
interrupt request
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