Epson S1C17001 Technical Manual page 342

Power supply
Sudden noise-induced power supply fluctuations will cause malfunctions. Consider the following precautions
to avoid such malfunctions.
(1) Form connections from the power supply to LV
terns possible.
(2) If a bypass capacitor is connected between LV
pins and the V pin should be as short as possible.
SS
Signal line location
• To prevent electromagnetically-induced noise caused by mutual inductance, avoid locating large-current sig-
nal lines near circuits susceptible to noise (e.g., clock inputs).
• Locating signal lines in parallel over significant distances or crossing high-speed signal lines will result in
mutual interference, noise, and malfunctions.
In particular, avoid positioning high-speed signal lines close to circuits susceptible to noise (e.g., clock input components).
Noise-induced malfunctions
Check the following three points if you suspect the presence of noise-induced IC malfunctions.
(1) DSIO pin
Low-level noise to this pin will cause a switch to Debug mode. The switch to Debug mode can be con-
firmed by the clock output from DCLK and a High signal from the DST2 pin.
For the product version, we recommend connecting the DSIO pin directly to HV
pin using a resistor not exceeding 10 kΩ.
The IC includes an internal pull-up resistor. The resistor has a relatively high impedance of 50 kΩ to 100
kΩ and is not noise-resistant.
(2) #RESET pin
Low-level noise to this pin will reset the IC. Depending on the input waveform, the reset may not proceed
correctly.
This is more likely to occur if, due to circuit design choices, the impedance is high when the reset input is High.
(3) LV , HV , V
DD DD SS
The IC will malfunction the instant noise falling below the rated voltage is input.
Incorporate countermeasures on the circuit board, including close patterns for circuit board power supply cir-
cuits, noise-filtering decoupling capacitors, and surge/noise prevention components on the power supply line.
Perform the inspections described above using an oscilloscope capable of observing waveforms of at least 200
MHz. It may not be possible to observe high-speed noise events with a low-speed oscilloscope.
If you detect potential noise-induced malfunctions while observing the waveform with an oscilloscope, recheck
with a low-impedance (less than 1 kΩ) resistor connecting the relevant pin to GND or to the power supply.
Malfunctions at that pin are likely if changes are visible, such as the malfunction disappearing, becoming less
frequent, or the phenomena changing.
The DSIO and #RESET input circuits described above detect input signal edges and are susceptible to malfunc-
tions induced by spike noise. This makes these digital signal pins the most susceptible to noise.
To reduce potential noise, keep the following two points in mind when designing circuit boards:
(A) It is important to use low impedance resistors when driving the signals, as described above. Avoid con-
necting impedance exceeding 1 kΩ (ideally, 0 Ω) to the power supply or GND. The signal lines connected
should be no longer than approximately 5 mm.
(B) Signals switching from 1 to 0 or 0 to 1 may generate noise if signal lines run parallel to other digital lines
on the circuit board.
The highest risk of noise occurs in configurations in which a line is sandwiched between multiple signal
lines that vary in synchrony. You can minimize noise effects by reducing the length of parallel sections (limit
to a few cm) or by increasing the separation (to at least 2 mm).
S1C17001 TECHNICAL MANUAL
power supply
APPENDIX C MOUNTING PRECAUTIONS
, HV , and the V
DD DD SS
/HV and V , the connection between the LV
DD DD SS
EPSON
pin with the shortest, thickest pat-
DD
or pulling up the DISO
DD
/HV
DD
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