0X5041: Watchdog Timer Status Register (Wdt_St) - Epson S1C17001 Technical Manual

17 WATCHDOG TIMER (WDT)

0x5041: Watchdog Timer Status Register (WDT_ST)

Register name Address Bit
Watchdog 0x5041 D7–2 –
Timer Status (8 bits)
D1
Register
(WDT_ST)
D0
D[7:2] Reserved
D1 WDTMD: NMI/Reset Mode Select Bit
Selects NMI or Reset generation on counter overflow.
1 (R/W): Reset
0 (R/W): NMI (default)
Setting this bit to 1 outputs a reset signal when the counter overflows. Setting to 0 outputs an NMI
signal.
D0 WDTST: NMI Status Bit
Indicates a counter overflow and NMI occurrence.
1 (R): NMI occurred (counter overflow)
0 (R): NMI did not occur (default)
This bit confirms that the watchdog timer was the source of the NMI.
The WDTST set to 1 is cleared to 0 by resetting the watchdog timer.
This is also set by a counter overflow if reset output is selected, but is cleared by initial resetting and
cannot be confirmed.
208
Name Function
reserved
WDTMD NMI/Reset mode select
WDTST NMI status
Setting
–
1 Reset 0 NMI
1 NMI oc- 0 Not oc-
curred
EPSON
Init. R/W Remarks
– – 0 when being read.
0 R/W
0 R
curred
S1C17001 TECHNICAL MANUAL