Epson S1C17001 Technical Manual page 231

18 UART
IrDA receive detection clock selection
The input pulse detection clock is selected from among the prescaler output clock PCLK-1/1 to PCLK-1/128
using IRCLK[2:0] (D[6:4]/UART_EXP register)
∗ IRCLK[2:0]: IrDA Receive Detection Clock Select Bits in the UART Expansion (UART_EXP) Register
(D[6:4]/0x4105)
This clock must be selected as a clock faster than the 8-bit timer or transfer clock sclk input via the SCLK pin.
The demodulation circuit treats Low pulses with a width of at least 2 IrDA receive detection clock cycles as
valid and converts them to 16 sclk cycle width Low pulses. Select the prescaler output clock to enable detection
of input pulses with a minimum width of 1.41 μs.
Serial data transfer control
Data transfer control in IrDA mode is identical to that for normal interfaces. For detailed information on data
format settings and data transfer and interrupt control methods, refer to the previous discussions.
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Table 18.8.1: IrDA receive detection clock selection
IRCLK[2:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
EPSON
Prescaler output clock
PCLK-1/128
PCLK-1/64
PCLK-1/32
PCLK-1/16
PCLK-1/8
PCLK-1/4
PCLK-1/2
PCLK-1/1
(Default: 0x0)
S1C17001 TECHNICAL MANUAL