Epson S1C17001 Technical Manual page 204

EIFT2 is set to 1 at the falling edge of the 100/10/1 Hz signals for which interrupts are permitted by the SWT
module. If EIEN2 is set to 1 here, the ITC sends an interrupt request to the S1C17 core. To prevent stopwatch
timer interrupts, set the EIEN2 to 0. EIFT2 is set to 1 by the interrupt signal from the SWT module regardless
of the EIEN2 setting (even if it is set to 0).
EILV2[2:0] sets the stopwatch timer interrupt level (0 to 7).
The S1C17 core accepts interrupts when the following conditions are satisfied:
• The interrupt enable bit has been set to 1.
• The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit has been set to 1.
• The stopwatch timer interrupt has been set to a higher interrupt level than that set for the PSR IL (interrupt
level).
• No other interrupt factors having higher precedence (e.g., NMI) are present.
For detailed information on these interrupt control registers and operations when interrupts occur, refer to "6
Interrupt Controller (ITC)."
Note: The following processes must be performed to manage the interrupt factor occurrence state
using the SWT module interrupt flag.
1. Set the ITC stopwatch timer interrupt trigger mode to level trigger mode.
2. Reset the SWT module interrupt flag SIF* within the interrupt processing routine after the
interrupt occurs (this also resets the ITC interrupt flag).
Interrupt vectors
The stopwatch timer interrupt vector numbers and vector addresses are listed below.
Vector number: 6 (0x06)
Vector address: 0x8018
S1C17001 TECHNICAL MANUAL
EPSON
16 STOPWATCH TIMER (SWT)
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