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11 PROGRaMMaBle TiMeR
PWM mode
Count clock
RLD register
CD register
Down-counter value
Compare match signal
Underflow signal
Timer output signal
Compare match interrupt
Underflow interrupt
Normal mode
Compare match signal
Underflow signal
Timer output signal
Underflow interrupt
11.6
16-bit timer mode (Timer 0 + 1, Timer 2 + 3)
In the S1C63004/008/016, Ch.A can be used as a 16-bit timer by coupling Timers 0 and 1. In the S1C63016, Ch.B
can also be used as a 16-bit timer by coupling Timers 2 and 3.
To use Ch.A (Timers 0 and 1) as a 16-bit timer, write "1" to the Timer 0 16-bit mode select register MOD16_A.
The 16-bit timer is configured with Timer 0 for low-order byte and Timer 1 for high-order byte as shown in Figure
11.6.1.
P10 port
EVIN_A
(P10)
Timer 0
PTRUN0
Run/Stop
Timer 0
clock
f
OSC1
PTPS0[3:0]
Clock
Timer 0 clock selection
manager
f
OSC3
f
/16 (2,048 Hz)
OSC1
Interrupt
Interrupt
control circuit
P11 port
TOUT_A
(P11)
Selector
PTOUT_A
Output control
In 16-bit timer mode, the Timer 0 register settings are effective for timer RUN/STOP control and count clock fre-
quency selection. The event counter function can also be used. Timer 1 uses the Timer 0 underflow signal as the count
clock, therefore, the Timer 1 RUN/STOP control and count clock frequency select registers become invalid. However,
the PWM output function must be controlled using the Timer 1 control register. Timer 1 output signal is automatically
selected for the TOUT_A output (the TOUT_A output select register is ineffective). The reload data must be preset
to Timer 0 and Timer 1 separately using each PTRSTx register.
11-6
0
7
6 5 4 3 2 1 0 7 6 5 4
Figure 11.
5.1 Generating PWM waveform
Timer 0 + 1
Timer 0 reset
Timer 1 reset
FCSEL_A
Timer function setting
PLPUL_A
Pulse polarity setting
EVCNT_A
Event counter
mode setting
1/2
Figure 11.
6.1 Configuration of 16-bit timer (Timer 0 + 1)
Seiko epson Corporation
7
6
3 2 1 0 7 6 5 4 3 2 1
CD register value
RLD register value + 1
Timer 0
Low-order 8 bits
Reload data register
PTRST0
RLD0[7:0]
PTRST1
8-bit down counter
Timer
control
circuit
Data buffer
PTD0[7:0]
Compare match signal
Compare data register
CD0[7:0]
PWM waveform
generator
S1C63003/004/008/016 TeChniCal Manual
[S1C63004/008/016]
Timer 1
High-order 8 bits
Reload data register
RLD1[7:0]
8-bit down counter
Data buffer
PTD1[7:0]
Comparator
Compare data register
CD1[7:0]
PTSEL1
PWM output selection
Underflow signal
(Rev. 1.1)
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