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Introduction
®
The Xilinx
LogiCORE™ IP CAN with Flexible
Data Rate (CAN FD) core is ideally suited for
automotive and industrial applications such as
automotive body control units, automotive test
equipment, instrument clusters, sensor
controls, and industrial networks. The core can
be used in standalone mode or connected to
Xilinx MicroBlaze™ processors or the Arm
Cortex-A9 processors in Zynq
Features
•
Designed to ISO 11898-1/2015
specification
[Ref 1]
•
Supports both CAN and CAN FD frames
•
Supports the CAN FD frame format
specified in the ISO 11898:2015
specification
[Ref 1]
•
Supports up to 64 byte CAN FD frames
•
Supports flexible data rates up to 8 Mb/s
•
Supports nominal data rates up to 1Mb/s
•
Up to three data bit transmitter delay
compensation
•
TX and RX mailbox buffers with
configurable depth
•
Two 64-deep RX FIFOs with 32 ID
Filter-Mask pairs
•
Message with lowest ID transmitted first
•
Supports TX message cancellation
•
Separate error logging for fast data rate
CAN FD v2.0
PG223 December 5, 2018
IMPORTANT:
FD protocol license before selling a device containing
the Xilinx CAN FD IP core.
®
®
-7000 SoCs.
Notes:
1.
2. Standalone driver details can be found in the SDK directory
3. For the supported versions of the tools, see the
www.xilinx.com
It is required to have a valid Bosch CAN
LogiCORE™ IP Facts Table
Core Specifics
Supported
(1)
Device Family
Zynq UltraScale+ MPSoC Architecture
Supported User
Interfaces
Resources
Performance and Resource Utilization web page
Provided with Core
Design Files
Example Design
Test Bench
Constraints File
Simulation
Model
Supported
(2)
S/W Driver
Tested Design Flows
Design Entry
For supported simulators, see the
Simulation
Xilinx Design Tools: Release Notes
Synthesis
Support
Provided by Xilinx at the
For a complete listing of supported devices, see the Vivado IP
.
catalog
(\Xilinx\SDK\<release_version>\data\embeddedsw\XilinxPro
cessorIPLib\drivers\canfd_version). Linux OS and driver
support information is available from the
Driver
Page.
Xilinx Design Tools: Release Notes
Send Feedback
IP Facts
UltraScale+™
UltraScale™
®
Zynq
-7000 SoC, 7 Series,
AXI4-Lite, APB
Encrypted RTL
Verilog
Verilog
XDC
Not Provided
Standalone and Linux
(3)
®
Vivado
Design Suite
Guide.
Vivado Synthesis
Xilinx Support web page
Linux CAN FD
Guide.
Product Specification
4
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