Register Summary: General-Purpose Timer 0; Register Details: General-Purpose Timer 0 - Analog Devices ADuCM310 Hardware Reference Manual

UG-549

REGISTER SUMMARY: GENERAL-PURPOSE TIMER 0

Table 226. Timer 0 Register Summary
Address Name
0x40000000 T0LD
0x40000004 T0VAL
0x40000008 T0CON
0x4000000C T0CLRI
0x40000010 T0CAP
0x4000001C T0STA

REGISTER DETAILS: GENERAL-PURPOSE TIMER 0

16-Bit Load Value Register
Address: 0x40000000, Reset: 0x0000, Name: T0LD
Table 227. Bit Descriptions for T0LD
Bits Bit Name
[15:0] LOAD
16-Bit Timer Value Register
Address: 0x40000004, Reset: 0x0000, Name: T0VAL
Table 228. Bit Descriptions for T0VAL
Bits Bit Name
[15:0] VAL
Control Register
Address: 0x40000008, Reset: 0x000A, Name: T0CON
Table 229. Bit Descriptions for T0CON
Bits Bit Name
[15:13] RESERVED
12 EVENTEN
[11:8] EVENT
7 RLD
[6:5] CLK
Description
16-bit load value register
16-bit timer value register
Control register
Clear interrupt register
Capture register
Status register
Description
Load value. The up/down counter is periodically loaded with this value if
periodic mode is selected (T0CON[3] = 1). LOAD writes during up/down
counter timeout events are delayed until the event has passed.
Description
Current count. Reflects the current up/down counter value. Value delayed
two PCLK cycles due to clock synchronizers.
Description
Reserved.
Event select. This bit enables and disables the capture of events. Used in
conjunction with the EVENT select range: when a selected event occurs,
the current value of the up/down counter is captured in T0CAP.
0: events are not captured.
1: events are captured.
Event select range. Timer event select range (0 to 15).
Reload control. RLD is only used for periodic mode; this bit allows the user
to select whether the up/down is reset only on a timeout event or also
when T0CLRI[0] is set.
1: up/down counter is reset when T0CLRI[0] is set.
0: up/down counter is only reset on a timeout event.
Clock select. These bits select a timer clock from the four available clock
sources.
00: PCLK.
01: HCLK.
10: LFOSC (32 kHz oscillator).
11: HFXTAL, if CLKCON0[11] = 1.
11: HFOSC, if CLKCON0[11] = 0.
Rev. C | Page 160 of 192
ADuCM310 Hardware Reference Manual
Reset Access
0x0000 RW
0x0000 R
0x000A RW
0x0000 W
0x0000 R
0x0000 R
Reset Access
0x0 RW
Reset Access
0x0 R
Reset Access
0x0 R
0x0 RW
0x0 RW
0x0 RW
0x0 RW