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LM3
VMEchip2 Board Status/Control Register
ADR/SIZ
BIT
7
NAME
RST
OPER
S/R
RESET
0 PSL
This register is the VMEchip2 board status/control register.
SYSFL
SCON
BF
ISF
RST
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This bit is cleared by an LM3 cycle on the VMEbus. This
bit is set when the local processor or a VMEbus master
writes a one to the LM3 bit in this register.
Local Bus: $FFF40104/VMEbus: $XXY2 (8 bits [5 used])
6
5
ISF
BF
R/W
R
0 PSL
1 PS
This bit is set when the VMEchip2 is driving the
SYSFAIL signal.
This bit is set if the VMEchip2 is system controller.
When this bit is high, the Board Fail signal is active.
When this bit is low, the Board Fail signal is inactive.
When this bit is set, the VMEchip2 drives SYSFAIL if the
inhibit SYSFAIL bit is not set.
When this bit is set, the VMEchip2 is prevented from
driving the VMEbus SYSFAIL signal line. When this bit
is cleared, the VMEchip2 is allowed to drive the VMEbus
SYSFAIL signal line.
This bit allows a VMEbus master to reset the local bus.
Refer to the note on local reset in the GCSR
Programming Model section, earlier in this chapter.
When this bit is set, a local bus reset is generated. This bit
is cleared by the local bus reset.
GCSR Programming Model
4
3
2
SCON
SYSFL
R
R
X
1 PSL
2
1
0
2-107
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