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PowerPC Architecture Compliance
SRR1—Save/Restore Register 1
1
Set to 1 for instruction fetch-related errors and 0 for load/store-related errors.
2–4
Set to 0.
10–15
Set to 0.
Other
Loaded from bits 16-31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
MSR—Machine State Register
IP
No change.
ME
Set to 0.
LE
Bit is copied from the ILE.
Other
Set to 0.
When using the load/store bus, the following registers are set:
DSISR—Data/Storage Interrupt Status Register
0–14
Set to 0.
15–16
Set to bits 29-30 of the instruction if X-form instruction and to 0b00 if D-form.
17
Set to Bit 25 of the instruction if X-form instruction and to Bit 5 if D-form.
18–21
Set to bits 21-24 of the instruction if X-form instruction and to bits 1-4 if D-form.
22–31
Set to bits 6-15 of the instruction.
DAR—Data Address Register
Set to the effective address of the data access that caused the interrupt.
Execution resumes at offset x'00200' from the base address indicated by MSR
7.3.7.3.3 Data Storage Interrupt. A data storage interrupt is never generated by the
hardware. However, the software may branch to this location as a result of either an
implementation-specific data TLB error or miss interrupt.
7.3.7.3.4 Instruction Storage Interrupt. An instruction storage interrupt is never
generated by the hardware, but the software may branch to this location as a result of an
implementation-specific instruction TLB error interrupt.
7.3.7.3.5 Alignment Interrupt. An alignment interrupt occurs as a result of one of the
following conditions:
• The operand of a floating-point load or store is not word aligned.
• The operand of a load/store multiple is not word aligned.
• The operand of a lwarx or stwcx is not word aligned.
• The operand of a load/store individual scalar instruction is not naturally aligned
when MSR
= 1.
LE
• An attempt to execute a multiple/string instruction is made when MSR
7-10
MPC823e REFERENCE MANUAL
.
RI
.
IP
= 1.
LE
MOTOROLA
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