Table of Contents
Advertisement
R
11.4.2.1.
VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
Use the following guidelines for the V
1. Traces should not cross anti-etch, for it greatly increases the return path for those signal traces.
This applies to USB 2.0 signals, high-speed clocks, and signal traces as well as slower signal
traces that might be coupling to them. USB signaling is not purely differential in all speeds (i.e.
the Full-speed Single Ended Zero is common mode).
2. Avoid routing of USB 2.0 signals 25 mils of any anti-etch to avoid coupling to the next split or
radiating from the edge of the PCB.
When breaking signals out from packages it is sometimes very difficult to avoid crossing plane splits or
changing signal layers, particularly in today's motherboard environment that uses several different
voltage planes. Changing signal layers is preferable to crossing plane splits if a choice has to be made
between one or the other.
If crossing a plane split is completely unavoidable, proper placement of stitching caps can minimize the
adverse effects on EMI and signal quality performance caused by crossing the split. Stitching capacitors
are small-valued capacitors (1 µF or lower in value) that bridge voltage plane splits close to where high
speed signals or clocks cross the plane split. The capacitor ends should tie to each plane separated by the
split. They are also used to bridge, or bypass, power and ground planes close to where a high-speed
signal changes layers. As an example of bridging plane splits, a plane split that separates V
V
3_3 planes should have a stitching cap placed near any high-speed signal crossing. One side of the
CC
cap should tie to V
current return path across plane splits. They minimize the impedance discontinuity and current loop area
that crossing a plane split creates.
11.4.2.2.
GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
Avoid anti-etch on the GND plane.
11.4.3.
USB Power Line Layout Topology
The following is a suggested topology for power distribution of Vbus to USB ports. Circuits of this type
provide two types of protection during dynamic attach and detach situations on the bus: inrush current
limiting (droop) and dynamic detach fly-back protection. These two different situations require both
bulk capacitance (droop) and filtering capacitance (for dynamic detach fly-back voltage filtering). It is
important to minimize the inductance and resistance between the coupling capacitors and the USB ports.
That is, capacitors should be placed as close as possible to the port and the power carrying traces should
be as wide as possible, preferably, a plane. A good "rule-of-thumb" is to make the power carrying traces
wide enough that the system fuse will blow on an over current event. If the system fuse is rated at 1amps
then the power carrying traces should be wide enough to carry at least 1.5 amps.
®
Intel
855GM/855GME Chipset Platform Design Guide
plane.
CC
5 and the other side should tie to V
CC
3_3. Stitching caps provide a high frequency
CC
I/O Subsystem
5 and
CC
209
Advertisement
Table of Contents
