Command Topology 1 Routing Guidelines; Figure 43. Command Routing For Topology 1; Table 32. Command Topology 1 Routing Guidelines - Intel 855GM Design Manual

System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration

Figure 43. Command Routing for Topology 1

GMCH
GMCH
Pin
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within
the DDR group, except clocks and strobes. There should be a minimum of 20 mils spacing to non-DDR
related signals. Command signals should be routed on inner layers with minimized external traces.
6.3.6.2.

Command Topology 1 Routing Guidelines

Table 32. Command Topology 1 Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DDR Signals
Package Length P1
Stub Lengths S0, S1
Trace Length L1 + S0 – GMCH Command Signal Ball to
First SO-DIMM Pad
Total Length L1 + L2 + L3 + S1 – Total Length from
GMCH Ball to Second SO-DIMM Pad
Total Length S0 + L2 + L3 + S1– Total SO-DIMM pad to
SO-DIMM pad spacing
Trace Length L4 – Second SO-DIMM Via to Parallel
Resistor Pad
Series Termination Resistor (Rs)
Parallel Termination Resistor (Rt)
98
P1 L1
S0
SO-DIMM0 PAD
Parameter
Rs
w
L2
L3
SO-DIMM1 PAD
Routing Guidelines
SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Daisy Chain with Parallel Termination
Ground Referenced
55 Ω ± 15%
Inner layers: 4 mils
Outer layers: 5 mils
2 to 1 (e.g. 8 mil space to 4 mil trace)
20 mils
500 mils +/- 250 mils
(See Table 35 for exact package lengths.)
Max = 0.25"
Min = 0.5 inch
Max = 4.0 inches
Min = 1.0"
Max = 7.0"
Max = 3.0"
Max = 1.5 inches
10 Ω ± 5%
56 Ω ± 5%
®
Intel 855GM/855GME Chipset Platform Design Guide
Vtt
w
L4
Rt
S1
R