Cpc Signal Routing Guidelines; Table 55. Cpc Signal Routing Guidelines - Intel 855GM Design Manual

R
7.3.7.2.

CPC Signal Routing Guidelines

Table 55. CPC Signal Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DDR Signals
Package Length P1
Trace Length S1 – Stub Length to Micro-DIMM
Connector
Trace Length L1 – GMCH Control Signal Ball to
Micro-DIMM Pad
Trace Length L2 – Micro-DIMM Pad to Parallel
Termination Resistor Pad
Trace Length TL0
Trace Length TL1
Trace Length TL2
Trace Length TL3
Parallel Termination Resistor (Rt)
Maximum Recommended Motherboard Via
Count Per Signal
Length Matching Requirements
NOTES:
1. Variance per topology for TL1, TL2, and TL3 + 10 mils.
®
Intel 855GM/855GME Chipset Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
Parameter Routing Guidelines
SMA[5,4,2,1], SMAB[5,4,2,1]
Point-to-Point with Parallel Termination
Ground Referenced
55 Ω ±15%
Inner layers: 4 mils
Outer layers: 5 mils
2 to 1 (e.g. 8 mil space to 4 mil trace)
20 mils
500 mils +/- 250 mils
(see Table 56 for exact package lengths.)
Max = 0.25"
Min = 0.25 inches
Max = 4.0 inches
Max = 2.0 inches
Min = 0.25 inches
Max = 1.5 inches
Min = 0.3 inches
Max = 0.7 inches
Min = 0.3 in Max = 0.7 in (see Figure 74 and Figure 75)
Min = 0.1 in Max = 0.5 in (see Figure 73)
Min = 0.1 inches
Max = 0.5 inches
56 Ω ± 5%
14
CPC to SCK/SCK# [5:0]
See length matching Section 7.3.7.3 and Figure 76 for details.
155