Figure 21. Processor Gtlref Voltage Divider Network - Intel 855GM Design Manual

R
(MCH_GTLREF) to be supplied to its HVREF[4:0] pins. The GTLREF voltage divider for both the
processor and GMCH cannot be shared. Thus, both the processor and GMCH must have their own
locally generated GTLREF networks. Figure 21 shows the recommended topology for generating
GTLREF for the processor using a R1 = 1 kΩ ± 1% and R2 = 2 kΩ ± 1% resistive divider.
Since the input buffer trip point is set by the 2/3*VCCP on GTLREF and to allow tracking of VCCP
voltage fluctuations, no decoupling should be placed on the GTLREF pin. The node between R1 and R2
(GTLREF) should be connected to the GTLREF pin of the processor with Zo = 55 Ω trace shorter than
0.5 inches. Space any other switching signals away from GTLREF with a minimum separation of 25
mils. Do not allow signal lines to use the GTLREF routing as part of their return path (i.e. do not allow
the GTLREF routing to create splits or discontinuities in the reference planes of the Processor System
Bus signals).
RSVD signal pins E26, G1, and AC1 are to be left unconnected on Intel® Pentium® M and Intel
Celeron M processor-based systems.

Figure 21. Processor GTLREF Voltage Divider Network

A recommended layout of GTLREF for the processor is shown in Figure 22. To avoid interaction with
PSB routing and power delivery, GTLREF's R1 and R2 components are placed next to each other on the
primary side of the motherboard and connected with a Zo = 55 Ω to the GTLREF pin on the processor.
The BGA ball lands on the primary side for the RSVD signal pins E26, G1, and AC1 are shown for
illustrative purposes and are not routed.
®
Intel 855GM/855GME Chipset Platform Design Guide
Intel Pentium M/Celeron M Front Side Bus Design Guidelines
+VCC +VCC
Zo=55 Ω trace Zo=55 Ω trace
R1 R1
1K 1K
1% 1%
GTLRE GTLRE
GTLRE GTLRE
R2 R2 (pin (pin
2K
2K
1% 1%
RSV RSV
(pin (pin
< 0.5" < 0.5"
RSV RSV
(pin (pin
Intel® Pentium®
Banias
M Processor
RSV RSV
(pin (pin
59