Table of Contents
Advertisement
R
Table 62. DVO Interface Trace Length Mismatch Requirements
Data Group
DVOBD [11:0]
DVOCD [11:0]
NOTES:
1. Data signals of the same group should be trace length matched to the clock within ±100 mil including package
lengths.
2. All length matching formulas are based on GMCH die-pad to DVO device pin total length. Package length
table are provided for all signals in order to facilitate this pad to pin matching.
8.3.2.
Package Length Compensation
As mentioned in Section 8.3.1, all length matching is done from GMCH die-pad to DVO connector pin.
The reason for this is to compensate for the package length variation across each signal group in order to
minimize timing variance. The 855GM chipset GMCH does not equalize package lengths internally as
some previous GMCH components have, and therefore, the 855GM chipset GMCH requires a length
matching process. See Table 64 for the DVO interface package lengths information.
Package length compensation should not be confused with length matching as discussed in the previous
section. Length matching refers to constraints on the minimum and maximum length bounds of a signal
group based on clock length, whereas package length compensation refers to the process of
compensating for package length variance across a signal group. There is of course some overlap in that
both affect the target length of an individual signal. Intel recommends that the initial route be completed
based on the length matching formulas in conjunction with nominal package lengths and that package
length compensation be performed as secondary operation.
8.3.3.
DVOB and DVOC Routing Guidelines
Table 63 provides the DVOB and DVOC routing guideline summary.
®
Intel
855GM/855GME Chipset Platform Design Guide
Signal Matching to
DVO Clock Strobes
Clock Strobe
Associated With the Group
± 100 mils
± 100 mils
Integrated Graphics Display Port
Clock Strobe Matching
DVOBCLK[1:0]
DVOCCLK[1:0]
Notes
± 10 mils
1,2
± 10 mils
1,2
169
Advertisement
Table of Contents
