Table of Contents
Advertisement
System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration
6.2.
Package Length Compensation
As mentioned in Section 6.1, all length matching is done GMCH die-pad to memory device pin. The
reason for this is to compensate for the package length variation across each signal group. The GMCH
does not equalize package lengths internally as some previous GMCH components have, and therefore,
the GMCH requires length matching.
Package length compensation should not be confused with length matching as discussed in the previous
section. Length matching refers to constraints on the min and max length bounds of a signal group
based on clock length, whereas package length compensation refers to the process of adjusting out
package length variance across a signal group. There is of course some overlap in that both affect the
target length of an individual signal. Intel recommends that the initial route be completed based on the
length matching formulas in conjunction with nominal package lengths and that package length
compensation be performed as secondary operation.
6.3.
Topologies and Routing Guidelines
The GMCH Double Data Rate (DDR) SDRAM system memory interface implements the low swing,
high-speed, terminated SSTL_2 topology. This section contains information related to the
recommended interconnect topologies and routing guidelines for each of the signal groups which
comprise the DDR interface. When implemented as defined, these guidelines will provide for a robust
DDR solution on a GMCH chipset based design.
6.3.1.
Clock Signals – SCK[5:0], SCK#[5:0]
The clock signal group includes the differential clock pairs SCK/SCK#[5:0]. The GMCH generates and
drives these differential clock signals required by the DDR interface; therefore, no external clock driver
is required for the DDR interface. The GMCH only supports unbuffered DDR SO-DIMMs; three
differential clock pairs are routed to each SO-DIMM connector. Table 23 summarizes the clock signal
mapping.
Table 23. Clock Signal Mapping
SCK/SCK#[2:0]
SCK/SCK#[5:3]
6.3.2.
Clock Topology Diagram
The GMCH provides 6 differential clock output pairs, or 3 clock pairs per SO-DIMM socket. The
motherboard clock routing topology is shown below for reference. Refer to the routing guidelines in
table 3 on the follow page for detailed length and spacing rules for each
should be routed as closely coupled differential pairs over the entire length. Spacing to other DDR
signals should not be less than 20 mils. Isolation spacing to non-DDR signals should be 25 mils.
78
Signal
Relative To
SO-DIMM0
SO-DIMM1
®
Intel
855GM/855GME Chipset Platform Design Guide
segment.
The clock signals
R
Advertisement
Table of Contents
