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R
7.3.6.
Command Signals – SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#,
SWE#
The Intel 855GM GMCH chipset command signals, SMA[12:0], SBA[1:0], SRAS#, SCAS#, and SWE#
clocked into the DDR SDRAMs using the clock signals SCK/SCK#[5:0]. The GMCH drives the
command and clock signals together, with the clocks crossing in the valid command window. A series
resistor is placed between the Micro-DIMM and Memory Down configuration to dampen the Micro-
DIMM to Memory Down
7.3.6.1.
Command Topology
The following is an example layout description based on layout studies on an 8 layer board. The
command signal routing should transition from an external layer to an internal signal layer (L1) under
the GMCH. At the via transition for the Micro-DIMM connector, the signal should transition to an
external layer (S1) and connect to the appropriate pad on the connector. After the Micro-DIMM
transition, continue to route the signal on the same internal layer (L2) until transitioning back to an
external layer at the series resistor Rs. At the via transition to the Rs resistor, parallel termination
resistor may be placed on the other side through the same via (L3). After the series resistor, the signal
should transition from the external layer to the same internal layer (TL0) and route until it is near the
SDRAMs. Via to another internal layer and split into two traces (TL1). Each trace routes to the middle
region of the SDRAM and then via to the external layer. Depending on the number of devices for
memory down, the command signal can route on the surface to the ball or pad (TL2) of one SDRAM (4
TSOP SDRAMs memory down) or two SDRAMs (8 BGA SDRAMs, TL4). If 8 BGAs, the signal will
continue on from the via on an internal layer (TL3) and go to the outer-most SDRAM. Via to the
external layer. Depending on the number of devices for memory down, the command signal can route
on the surface (TL4) to the ball or pad of one SDRAM (4 TSOP SDRAMs) or two SDRAM (8 BGAs).
All internal and external signals should be ground referenced to keep the path of the return current
continuous.
Resistor packs are acceptable for the series and parallel command termination resistors but command
signals cannot be placed within the same R-packs as data, strobe, or control signals. Figure 68, Figure
69 and Table 52 below depict the recommended topology and layout routing guidelines for the DDR-
SDRAM command signals routing to the Micro-DIMM and Memory Down.
®
Intel
855GM/855GME Chipset Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
resonance.
145
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