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11.
I/O Subsystem
11.1.
IDE Interface
This section contains guidelines for connecting and routing the Intel 82801DBM ICH4-M IDE interface.
The ICH4-M has two independent IDE channels. This section provides guidelines for IDE connector
cabling and motherboard design, including component and resistor placement, and signal termination for
both IDE channels. The ICH4-M has integrated the series resistors that have been typically required on
the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors. While it is not
anticipated that additional series termination resistors will be required, OEMs should verify motherboard
signal integrity through simulation. Additional external 0Ω resistors can be incorporated into the design
to address possible noise issues on the motherboard. The additional resistor layout increases flexibility
by offering stuffing options at a later date.
The IDE interface can be routed with 5-mil traces on 7-mil spaces, and must be less than 8 inches long
(from ICH4-M to IDE connector). Additionally, the maximum length difference between the shortest
data signal and the longest strobe signal of a channel is 0.5 inches.
11.1.1.
Cabling
The cabling guidelines below must be followed:
•
Length of cable: Each IDE cable must be equal to or less than 18 inches.
•
Capacitance: Less than 35 pF.
•
Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive is
placed on the cable it should be placed at the end of the cable. If a second drive is placed on the
same cable, it should be placed on the next closest connector to the end of the cable (6 inches
away from the end of the cable).
•
Grounding: Provide a direct low impedance chassis path between the motherboard ground and
hard disk drives.
•
ICH4-M Placement: The ICH4-M must be placed equal to or less than 8 inches from the ATA
connector(s).
®
Intel
855GM/855GME Chipset Platform Design Guide
I/O Subsystem
195
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