Sdqs To Clock Length Matching Requirements; Table 26. Memory Data Signal Group Routing Guidelines - Intel 855GM Design Manual

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Table 26. Memory Data Signal Group Routing Guidelines

Signal Group
Motherboard Topology
Reference Plane
Characteristic Trace Impedance (Zo)
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
Minimum Isolation Spacing to non-DDR Signals
Package Length P1
Trace Length L1 – GMCH Signal Ball to Series
Termination Resistor Pad
Trace Length L2 – Series Termination Resistor Pad to
First SO-DIMM Via
Stub Length S0, S1 – Stub from Via to SO-DIMM Pad
Total Length L1 + L2 + S0 – Total Length from GMCH
to First SO-DIMM Pad
Total Length L1 + L2 + L3 + S1 – Total Length from
GMCH to Second SO-DIMM Pad
Total Length S0 + L3 + S1– Total SO-DIMM pad to SO-
DIMM pad spacing
Trace Length L4 – Last SO-DIMM Via to Parallel
Termination Resistor Pad
Series Termination Resistor (Rs)
Parallel Termination Resistor (Rt)
Length Matching Requirements
NOTES:
1. Power distribution vias from Rt to Vtt are not included in this count.
2. The overall minimum and maximum length to the SO-DIMM must comply with clock length matching
requirements.
3. It is possible to route using 4 vias if trace segments L2 and L4 are routed on the same external layer as the
associated SO-DIMM, for example if L2 is on the same layer as SO-DIMM0.
6.3.4.2.

SDQS to Clock Length Matching Requirements

The first step in length matching is to determine the SDQS length range based on the SCK/SCK#
reference length defined previously. The total length of the SDQS strobe signals, including package
length, between the GMCH die-pad and the SO-DIMMs must fall within the range defined in the
formulas below. See the clock Section for the definition of the clock reference length. Refer to Figure
®
Intel 855GM/855GME Chipset Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration
Parameter Definition
SDQ[71:0], SDQS[8:0], SDM[8:0]
Daisy Chain with Parallel Termination
Ground Referenced
55 Ω +/- 15%
Inner layers: 4 mils
Outer layers: 5 mils
SDQ/SDM: 2 to 1 (e.g. 8 mil space to 4 mil trace)
SDQS: 3 to 1 (e.g. 12 mil space to 4 mil trace)
20 mils
700 mils +/- 300 mils (See Table 28 for details)
Min = 0.5"
Max = 3.75"
Max = 0.75"
Max = 0.25"
Min = 0.5"
Max = 4.0"
Min = 0.75"
Max = 4.5"
Min = 0.25"
Max = 1.0"
Max = 1.0"
10 Ω ± 5%
56 Ω ± 5%
SDQS to SCK/SCK# See length matching Section 6.3.4.2
SDQ/SDM to SDQS, to +/- 25mils, within each byte lane
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