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I/O Subsystem
11.7.
FWH
The following provides general guidelines for compatibility and design recommendations for supporting
the FWH device. The majority of the changes will be incorporated in the BIOS. Refer to the FWH BIOS
Specification or equivalent.
11.7.1.
FWH Decoupling
Refer to section 13.5.6 for more details.
11.7.2.
In Circuit FWH Programming
All cycles destined for the FWH will appear on PCI. The ICH4-M hub interface to PCI Bridge will put
all CPU boot cycles out on PCI (before sending them out on the FWH interface). If the ICH4-M is set
for subtractive decode, these boot cycles can be accepted by a positive decode agent on the PCI bus.
This enables the ability to boot from a PCI card that positively decodes these memory cycles. In order to
boot from a PCI card, it is necessary to keep the ICH4-M in subtractive decode mode. If a PCI boot card
is inserted and the ICH4-M is programmed for positive decode, there will be two devices positively
decoding the same cycle.
11.7.3.
FWH INIT# Voltage Compatibility
The FWH INIT# signal trip points need to be considered because they are NOT consistent among
different FWH manufacturers. The INIT# signal is active low. Therefore, the inactive state of the ICH4-
M INIT# signal needs to be at a value slightly higher than the V
The inactive state of this signal is typically governed by the formula V_CPU_IO(min) – noise margin.
Therefore if the V_CPU_IO(min) of the processor is 1.60 V, the noise margin is 200 mV and the V
min spec of the FWH INIT# input signal is 1.35 V, there would be no compatibility issue because 1.6 V
– 0.2 V = 1.40 V which is greater than the 1.35 V minimum of the FWH. If the V
1.45 V, then there would be an incompatibility and logic translation would need to be used. The
examples above do not take into account any noise that may be encountered on the INIT# signal. Care
must be taken to ensure that the V
where it is necessary to use translation logic, refer to Section 4.1.4.7.
The solution assumes that level translation is necessary. The figure in Section 4.1.4.7 implements a
solution for the ICH4-M FWH signal INIT#. Trace lengths and resistor values can be found in Table 16.
The Voltage Translator circuitry is shown in Figure 16. It is strongly recommended that any system that
implements a FWH should have its INIT# input connected to the ICH4-M.
216
min specification is met with ample noise margin. In applications
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Intel
855GM/855GME Chipset Platform Design Guide
min FWH INIT# pin specification.
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min of the FWH was
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