Figure 104. Smbus 2.0/Smlink Protocol - Intel 855GM Design Manual

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micro-controller to perform various functions. For example, the slave write interface can reset or wake a
system, generate SMI# or interrupts, and send a message. The slave read interface can read the system
power state, read the watchdog timer status, and read system status bits.
Both the SMBus Host Controller and the SMBus Slave Interface obey the SMBus 1.0 protocol, so the
two interfaces can be externally wire-OR'ed together to allow an external management ASIC (such as
Intel 82562EM 10/100 Mbps Platform LAN Connect) to access targets on the SMBus as well as the
ICH4-M Slave Interface. Additionally, the ICH4-M supports slave functionality, including the Host
Notify protocol, on the SMLink pins. Therefore, in order to be fully compliant with the SMBus 2.0
specification (which requires the Host Notify cycle), the SMLink and SMBus signals must be tied
together externally. This is done by connecting SMLink[0] to SMBCLK and SMLink[1] to SMBDATA.

Figure 104. SMBUS 2.0/SMLink Protocol

Host Controller and
Slave Interface
Intel ®
Intel does not support external access of the ICH4-M's Integrated LAN Controller via the SMLink
interface. Also, Intel does not support access of the ICH4-M's SMBus Slave Interface by the ICH4-M's
SMBus Host Controller. Refer to the Intel
Datasheet for full functionality descriptions of the SMLink and SMBus interface.
®
Intel 855GM/855GME Chipset Platform Design Guide
SMBus
ICH4
SMLink
Wire OR
(optional)
SPD Data
Temperature on
Thermal Sensor
SMBCLK
SMBDATA
SMLink0
SMLink1
Motherboard
LAN
Controller
®
82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
I/O Subsystem
Network
Interface Card
on PCI Bus
Microcontroller
SMbus-SMlink_IF
213