Cpc Signals - Sma[5,4,2,1], Smab[5,4,2,1]; Table 54. Cpc Signal To So-Dimm Micro-Dimm And/Or Memory Down Mapping - Intel 855GM Design Manual

System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration
7.3.7. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1]
The GMCH drives the CPC and clock signals together, with the clocks crossing in the valid control
window. The GMCH provides one set of CPC signals for the Micro-DIMM slot and one set for the
Memory Down configuration.
Refer to Table 49 for the CKE and CS# signal to Micro-DIMM mapping.

Table 54. CPC Signal to SO-DIMM Micro-Dimm and/or Memory Down Mapping

Signal
SMA[1]
SMA[2]
SMA[4]
SMA[5]
SMAB[1]
SMAB[2]
SMAB[4]
SMAB[5]
The following is an example layout description based on layout studies on an 8-layer board. The CPC
signals should transition from an external layer to an internal signal layer (L1) under the GMCH. If the
signal is going to the Micro-DIMM connector, route the signal on the internal layer and via to the
external layer and connect to the appropriate pad on the connector (S1). If the signal is going to the
SDRAMs, route the signal on the internal layer until transitioning back to an external layer at the parallel
termination (L2). When it is close to the SDRAMs, the signal should via to another internal layer and
split into two traces (TL0). Each trace routes to the middle region of the SDRAM (TL1) and via to the
external layer. Depending on the number of devices for memory down, the CPC signal can be routed on
the surface (TL2) to the ball or pad of one SDRAM or two SDRAMs. If 8 BGAs, the signal will
continue on from the via on an internal layer (TL2 on 8 BGA devices topology) and go to the center
region of the outer-most SDRAM then via to the external layer. Depending on the number of devices for
memory down, the CPC signal can be routed on the surface (TL3 on 8 BGA devices topology) to the ball
or pad of one SDRAM device (4 TSOP SDRAMs) or two SDRAMs (8 BGAs).
External trace lengths should be minimized. All internal and external signals should be ground reference
to keep the path of return current continuous. Intel suggests that all control signals be routed on the same
internal layer.
Resistor packs are acceptable for the parallel (Rt) control termination resistors, but control signals
cannot be placed within the same R pack as the data or command signals. Figure 74, Figure 75, Figure
76, and Table 55 below depict the recommended topology and layout routing guidelines for the DDR-
SDRAM control signals.
152
Relative To Pin
Micro-DIMM Micro-DIMM pad #85
Micro-DIMM Micro-DIMM pad #84
Micro-DIMM Micro-DIMM pad #82
Micro-DIMM Micro-DIMM pad #81
Mem Down Mem Device Pin
Mem Down Mem Device Pin
Mem Down Mem Device Pin
Mem Down Mem Device Pin
Intel
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855GM/855GME Chipset Platform Design Guide
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