Video Signal System (Dvp-41 Board) - Sony HDCAM HDW-F900R Maintenance Manual

1-26-3. Video Signal System (DVP-41 Board)

. Signal processing during recording
The 74 MHz 20-bit Y-signal and the PbPr signal that are
supplied from the camera circuit of the DCP-43 board to
the DVP-41 board, are passed through the DF.F (IC140 to
IC142) and then input to the REGALO (IC160) rate
converter circuit. The 74 MHz 20-bit Y-signal and the
PbPr signal are down-sampled by the rate converter circuit
to the 46 MHz 20-bit multiplexed Y/PbPr signal. At the
same time, the signal is sampled by every other pixel. The
output signal from the rate converter circuit is sent to the
bit rate reduction circuit of the MICKY-A (IC300) and
MICKY-B (IC350) via the BUS SWITCH (IC302). In the
bit rate reduction circuit, the Y-signal is grouped into the
signal unit of 8 pixels (H) x 8 pixels (V) and the PbPr
signal is grouped into the signal unit of 4 pixels (H) x 8
pixels (V), to which shuffling processing (i.e., the adjacent
blocks are assigned to the six segments) is implemented.
After the shuffling processing, the DCT coefficient is
calculated from the data of the respective blocks so that the
quantization and VLC (Variable Length Coding) process-
ing are performed. The compression rate here is 1/4.4.
Combining the compression rate of 1/1.6 for down sam-
pling at FIL (IC160), the total compression rate is about 1/
7. The compressed video data passes through DF.F (IC403
and IC404) and is sent to NECCY (IC400) that is the error
correction encoder circuit. In the error correction encoder
circuit, the compressed picture data receives the following
processes.
. Generation of the outer parity and inner parity
. Addition of the SYNC/ID code
. Generation of SYNC block
At the same time, the serial audio data that is supplied
from the audio circuit of the FP-152 board passes through
the SEL (IC406) and is input to the error correction
encoder circuit in ECC (IC400). In the error correction
encoder circuit, the serial audio data receives the processes
of generating the outer parity and inner parity, addition of
the SYNC/ID code and the SYNC block is generated.
After the serial audio data is multiplexed with the picture
data, the multiplexed signal is sent to the RF system circuit
in the EQ-88G board as two-channel serial data.
. Signal processing during playback
The playback data that is supplied from the RF system
circuit of the EQ-88G board to the DVP-41 board, passes
through the BUS SWITCH (IC501), and is input to the
error correction decoder circuit of the ADAM-HS (IC500).
1-66
In the error correction decoder circuit, the errors that are
occured during the recording and playback processes are
corrected. An error flag is added to the errors that could
not be corrected by the error correction decoder circuit so
that error concealment can be performed by the error
concealment circuit of the CNC (IC700). At the same time,
the audio data is separated in the error correction decoder
circuit, and the separated audio data is sent to the audio
circuit of the FP-152 board as the playback serial audio
data.
The playback video data that is supplied from the error
correction decoder circuit, passes through the BUS
SWITCH (IC506 and IC507) and is sent to the bit rate
reduction decoder circuit that consists of MINNY-A
(IC600) and MINNY-B (IC650). In the bit rate reduction
decoder circuit, the reverse processing of the bit rate
reduction circuit is performed. The 46 MHz 20-bit Y/PbPr
signal is generated by the bit rate reduction decoder circuit,
and is sent to the error concealment circuit of CNC
(IC700). In the error concealment circuit, the correct data
is judged for error data for which the error flag is set, from
the peripheral pixels and the data of the previous frame,
and the error concealment is performed. After the error
concealment, the data passes through the BUS SWITCH
(IC161) and is input to the rate converter circuit of REGA-
LO (IC160). In the rate converter circuit, the 46 MHz 20-
bit Y/PbPr signal is up-sampled to the 74 MHz 20-bit Y-
signal and to the PbPr signal, which are then sent to the
camera system circuit in the DCP-43 board.
. Clock signal and timing reference signal processing
Two types of clock signals (74 MHz and 46 MHz) are used
in the video system circuit of the DVP-41 board.
The 74 MHz clock is supplied from the camera system
circuit of the DCP-43 board to the DVP-41 board where it
is phase-compensated by the 74M CLOCK DRIVE
(IC101), and is then distributed to the respective ICs. The
46 MHz clock is generated by TG (IC200) of the DVP-41
board as the clock that is synchronous with the frame pulse
supplied from the camera system circuit of the DCP-43
board. The 46 MHz clock is phase-compensated by the
46M CLOCK DRIVE (IC203) and is then distributed to
the respective ICs.
The timing reference signals are generated by TG (IC200)
of the DVP-41 board for the respective ICs, from the frame
pulse and the HD pulse that are supplied from the camera
system circuit of the DCP-43 board. However, the timing
reference signal of the playback video data RAGALO
(IC160) is supplied from the camera system circuit of the
DCP-43 board.
HDW-F900R/V1 (E)