Sony HDCAM HDW-F900R Maintenance Manual page 88

2-3 Pull-down down converter board
(DC-139 board : HKDW-902R)
The circuit board DC-139 performs the following process-
es using down-converter board that has the 2-3 pull-down
function.
The 1125HD signal (10-bit parallel component Y/C signal)
input from the DCP-43 board is input to IC8, and 59.94i/
50i/29.97PsF/25PsF is converted into through as a result of
the 2-3 pull-down correction, and 23.98PsF into 59.94i.
The HD signal output from IC8 is down-converted to the
D1 parallel signal (component Y/C digital parallel SD
signal) at IC227, and output as the composite signal via the
encoder (IC401).
Also, the D1 parallel signal is multiplexed with the
DigitalAudio signal at IC603, and output as the SDI signal.
The composite signal is output to the TEST OUT connec-
tor via the CharacterMIX circuit on the DCP-43 board, and
at the same time, output to the VIDEO OUT connector via
the 75Z driver (Q605 to Q611) on the DC-139 board.
The VIDEO OUT connector can also output the SDI
signal. Whether to output the composite signal or the SDI
signal is selected from the menu (OPERATION menu →
OUTPUT SEL screen → SD REAR BNC OUT).
(For details, refer to "Section 4-4 OPERATION Menu".)
For the 23.98PsF/24PsF HD signal, the HD-Y signal, to
which the 2-3 pull-down correction was applied at IC8, can
be displayed on VF, and it is selected using OPERATION
menu → OUTPUT SEL screen → VF Y 2-3PULLDOWN.
(For details, refer to "Section 4-4 OPERATION Menu".)
1-78
Picture cache board (MY-99 board : HKDW-703)
The circuit board MY-99 implements the LOOP REC and
performs the following processes.
The signal format of the compressed video data and the
audio data that are supplied from the video system circuit
of the DVP-41 board during the LOOP REC mode or the
INTERVAL REC mode, is converted at the LOOP MEM-
ORY (IC201) to be suitable for storage in the SDRAM.
The video data is then written sequentially in the SDRAM
(IC301 to IC308) and the audio data is written in the
MEMORY (IC309 and IC310). The stored data is read
from the memory in accordance with the specified timing
and returned to the original signal format by the LOOP
MEMORY (IC201) again. Then the video data passes
through the BUS SWITCH (IC202 and IC204) and the
audio data passes through the SEL (IC207) respectively,
and are sent to the video system circuit of the DVP-41
board. The TC data is handled in the same manner as the
audio data and is stored in the MEMORY (IC309 and
IC310).
Control of the read/write timings of the SDRAM is
performed by commands supplied from the I/O EXPAND-
ER (IC103). These are controlled by the system control
circuit of the SS CPU (IC1) of the SS-92G board.
Regarding the clock signal for the SDRAM, the SDRAM
(IC301 to IC308) for video data receives the 46.360 MHz
clock coming from the video system circuit of the DVP-41
board after it is phase-compensated by the CLOCK
DRIVER (IC141) of the MY-99 board. The MEMORY
(IC309 and IC310) for audio data receives the clock from
the LOOP MEMORY (IC201).
HDW-F900R/V1 (E)