Sony HDCAM HDW-F900R Maintenance Manual page 89

Slow shutter and image inverter board
(PM-23 board : HKDW-905R)
The PM-23 board is located between the output side and
the input side of the digital pixel addition IC (IC1017) on
the DCP-43 board, and performs the following operations:
. Slow shutter
The timing pulse (HTSG) that is output from the FPGA
(IC1) on the PM-23 board blocks the CCD read pulse
output from the TG-256 board. Therefore, the signal
charge is accumulated in the CCD.
At the same time, the timing pulse (L_OPB) that is output
from the FPGA (IC1) turns off SW_IC (IC1014, IC1015)
on the DCP-43 board.
In the mean time, the digital video signal written in the
SDRAM_A (IC2, IC3) on the PM-23 board is output to the
digital process IC (IC1019), and performs image interpola-
tion for the accumulated time.
The timing pulse (HTSG) from the PM-23 board cancels
blocking of the CCD read pulse, and the timing pulse
(L_OPB) turns on SW_IC (IC1014, IC1015) on the DCP-
43 board.
At this time, the digital video signal is written in the
SDRAM_A (IC2, IC3). The sequential operation of these
steps performs the image accumulation and interpolation
(slow shutter).
BI BOARD
R CH
CCD
G CH
CCD
B CH
CCD
HDW-F900R/V1 (E)
DCP BOARD
PA BOARD
CDS
VA
CDS
AD
CDS
CCD READ OUT PULSE
CCD
TG
TG BOARD
. Image inversion
The timing pulse (L_OPB) that is output from the FPGA
(IC1) on the PM-23 board turns off SW_IC (IC1014,
IC1015) on the DCP-43 board.
This process separates the digital pixel addition IC
(IC1017) and the digital process IC (IC1019) on the DCP
board.
The digital video signal is written to the SDRAM_A (IC2,
IC3) in this state. The digital video signal is then written to
SDRAM_B (IC4, IC5) in the next frame.
At the same time, the digital video signal accumulated in
SDRAM_A (IC2, IC3) is read in the reverse order from the
timing it was written, and then output to the digital process
IC (IC1019) on the DCP-43 board.
The digital video signal is then written to SDRAM_A
(IC2, IC3) in the next frame.
At the same time, the digital video signal accumulated in
SDRAM_B (IC4, IC5) is read in the reverse order from the
timing it was written, and then output to the digital process
IC (IC1019) on the DCP-43 board.
The sequential operation of these steps performs the image
inversion process.
PM-23 BOARD
IC1
F_ACM
(FPGA)
DEFCON (FPGA)
IC1017
PIXEL-
ADDITION
DEFECTION
SYSTEM
IC4, IC5
SDRAM_B
IC2, IC3
SDRAM_A
IC1019
SCVP
Fig.4 PM-23 board circuit diagram
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