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7.1.
THE PENTIUM
Most of the Pentium II processor signals use a variation of the low voltage Gunning
Transceiver Logic (GTL) signaling technology.
The Pentium II processor system bus specification is similar to the GTL specification, but
has been enhanced to provide larger noise margins and reduced ringing. The improvements
are accomplished by increasing the termination voltage level and controlling the edge rates.
Because this specification is different from the standard GTL specification, it is referred to as
GTL+ in this document. For more information on GTL+ specifications, see Chapter 8, GTL+
Interface Specifications or AP-585, Pentium
243330).
The GTL+ signals are open-drain and require termination to a supply that provides the high
signal level. The GTL+ inputs use differential receivers which require a reference signal
(V
). Termination (usually a resistor at each end of the signal trace) is used to pull the bus
REF
up to the high voltage level and to control reflections on the transmission line. V
by the receivers to determine if a signal is a logical 0 or a logical 1, and is generated on the
S.E.C. cartridge for the processor core. The processor contains termination resistors that
provide termination for one end of the Pentium II processor system bus. See Table 8-1 for the
bus termination voltage specifications for GTL+. Local V
the motherboard for all other devices on the GTL+ system bus. Figure 7-1 is a schematic
representation of GTL+ bus topology with the Pentium II processor.
Pentium
Processor
The GTL+ bus depends on incident wave switching. Therefore timing calculations for GTL+
signals are based on flight time as opposed to capacitive deratings. Analog signal simulation
of the Pentium II processor system bus including trace lengths is highly recommended when
designing a system with a heavily loaded GTL+ bus. See Intel's world wide web page
(http://www.intel.com) to download the buffer models, Pentium
Models, IBIS Format (Electronic Form).
ELECTRICAL SPECIFICATIONS
®
II PROCESSOR SYSTEM BUS AND V
®
II Processor GTL+ Guidelines (Order Number
No Stubs
II
ASIC
®
Figure 7-1. GTL+ Bus Topology
CHAPTER 7
copies should be generated on
REF
ASIC
Pentium II
Processor
®
II Processor I/O Buffer
REF
is used
REF
000916
7-1
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