Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
Page 4 Detailed descriptions of the CPU and instruction set RX Family Series REJ09B0435 Software User’s manual: Software Application Note Examples of applications and sample programs — — Renesas Preliminary report on the specifications of a product, — — Technical Update document, etc.
Page 5 2. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below. X.X.X ...
Page 6 3. List of Abbreviations and Acronyms Abbreviation Full Form ACIA Asynchronous Communication Interface Adapter bits per second Cyclic Redundancy Check Direct Memory Access DMAC Direct Memory Access Controller Global System for Mobile Communications Hi-Z High Impedance IEBus Inter Equipment Bus Input / Output IrDA Infrared Data Association...
Page 7: Table Of Contents
Contents Contents ................................7 Overview ..............................28 Features ................................28 1.1.1 Applications ............................. 28 1.1.2 Outline of Specifications .......................... 29 List of Products ..............................32 Block Diagram ..............................34 Pin Assignments ..............................35 Pin Functions..............................49 CPU ................................54 Features ................................54 Register Set of the CPU ............................
Page 8 2.5.4.1 Data Arrangement in Registers ......................73 2.5.4.2 Data Arrangement in Memory ......................73 2.5.5 Notes on Arrangement of Instruction Code ..................... 73 Vector Table ..............................74 2.6.1 Fixed Vector Table ........................... 74 2.6.2 Relocatable Vector Table ......................... 75 Operation of Instructions ........................... 76 2.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions ......
Page 9 Resets ............................... 154 Overview ................................. 154 Register Descriptions ............................156 6.2.1 Reset Status Register (RSTSR) ......................156 6.2.2 Reset Control/Status Register (RSTCSR) ....................157 Operation ................................. 158 6.3.1 Pin Reset ..............................158 6.3.2 Deep Software Standby Reset ........................ 158 6.3.3 Watchdog Timer Reset ...........................
Page 10 8.2.8 Deep Standby Interrupt Flag Register (DPSIFR) ................... 184 8.2.9 Deep Standby Interrupt Edge Register (DPSIEGR) ................185 8.2.10 Reset Status Register (RSTSR) ......................186 8.2.11 Deep Standby Backup Register (DPSBKRy) (y = 0 to 31) ..............186 Multi-Clock Function ............................187 Module Stop Function .............................
Page 11 9.1.6 Interrupts ..............................204 9.1.7 Unconditional Trap ..........................204 Exception Handling Procedure........................205 Acceptance of Exceptions ..........................207 9.3.1 Timing of Acceptance and Saved PC Values ..................207 9.3.2 Vector and Site for Saving the Values in the PC and PSW ..............208 Hardware Processing for Accepting and Returning from Exceptions .............
Page 12 10.4.2.1 Interrupt Status Flag in Edge Detection .................... 243 10.4.2.2 Interrupt Status Flag in Level Detection .................... 244 10.4.3 Selecting Interrupt Request Destinations ....................246 10.4.4 Determining Priority ..........................248 10.4.5 Fast Interrupt ............................248 10.4.6 External Interrupts ..........................249 10.5 Non-maskable Interrupt Operation ........................
Page 13 11.5.2.2 Page Access ............................293 11.5.3 Insertion of Recovery Cycles ......................... 295 11.5.4 Write Buffer Function ..........................296 11.5.5 Notes on Usage ............................297 11.5.5.1 Limitations at the Time of Normal and Page Access ................ 297 11.5.5.2 Prohibition of Access that Spans Areas of Address Space ..............297 11.5.5.3 Restrictions in Relation to RMPA and String-Manipulation Instructions .........
Page 14 12.3.6 Suspending, Restarting, and Canceling DMA Transfer ................. 328 12.3.7 DMA Activation Source ........................329 12.3.7.1 Software Trigger ..........................329 12.3.7.2 Interrupt Signals on External Pins and Peripheral Function Interrupts ..........329 12.3.8 Channel Arbitration ..........................330 12.3.9 Reload Function ............................. 330 12.3.10 Rotate ..............................
Page 15 13.6.1 Normal Transfer ............................. 363 13.6.2 Chain Transfer ............................364 13.6.3 Chain Transfer when Counter = 0 ......................365 13.7 Interrupt Source ............................... 367 13.8 Low-Power Consumption ..........................367 13.8.1 Setting the DTC Module Start Register ....................367 13.9 Usage Notes ..............................367 13.9.1 Transfer Data Start Address/Transfer Source Address/Transfer Destination Address ......
Page 16 14.3.11 Port A (PA) ............................421 14.3.12 Port B (PB) ............................. 425 14.3.13 Port C (PC) ............................. 428 14.3.14 Port D (PD) ............................431 14.3.15 Port E (PE) ............................. 431 14.3.16 Port F (PF) .............................. 432 14.3.17 Port G (PG) ............................434 14.3.18 Port H (PH) ............................
Page 17 15.8 Operation Timing ............................513 15.8.1 Input/Output Timing ..........................513 15.8.2 Interrupt Signal Timing .......................... 517 15.9 Usage Notes ..............................519 15.9.1 Module Stop Function Setting........................ 519 15.9.2 Input Clock Restrictions ......................... 519 15.9.3 Caution on Cycle Setting ........................520 15.9.4 Conflict between TPUm.TCNT Write and Clear Operations ..............
Page 18 17. 8-Bit Timer (TMR) ............................. 561 17.1 Overview ................................. 561 17.2 Register Descriptions ............................565 17.2.1 Timer Counter (TCNT) .......................... 566 17.2.2 Time Constant Register A (TCORA) ..................... 566 17.2.3 Time Constant Register B (TCORB) ..................... 567 17.2.4 Timer Control Register (TCR) ....................... 568 17.2.5 Timer Counter Control Register (TCCR) ....................
Page 19 18.2.3 Compare Match Timer Control Register (CMCR) ................. 591 18.2.4 Compare Match Counter (CMCNT) ...................... 592 18.2.5 Compare Match Constant Register (CMCOR) ..................592 18.3 Operation ................................. 593 18.3.1 Periodic Count Operation ........................593 18.3.2 CMCNT Count Timing .......................... 593 18.4 Interrupts .................................
Page 20 20.2.1 Receive Shift Register (RSR) ......................... 614 20.2.2 Receive Data Register (RDR) ........................ 614 20.2.3 Transmit Data Register (TDR) ....................... 614 20.2.4 Transmit Shift Register (TSR) ....................... 615 20.2.5 Serial Mode Register (SMR) ........................615 20.2.6 Serial Control Register (SCR) ........................ 619 20.2.7 Serial Status Register (SSR) ........................
Page 21 20.7.5 Writing Data to TDR ..........................674 20.7.6 Restrictions on Clock Synchronous Transmission ................. 675 20.7.7 Restrictions on Using DTC or DMAC ....................675 20.7.8 SCI Operations during Power-Down State .................... 675 20.7.9 External Clock Input in Clock Synchronous Mode ................678 21.
Page 22 22.3.3 Master Transmitter Operation ........................ 729 22.3.4 Master Receiver Operation ........................733 22.3.5 Slave Transmitter Operation ........................738 22.3.6 Slave Receiver Operation ........................741 22.4 SCL Synchronization Circuit .......................... 744 22.5 Facility for Delaying SDA Output ........................745 22.6 Digital Noise-Filter Circuits ..........................746 22.7 Address Match Detection ..........................
Page 23 22.15.5 Notes when Communication is Restarted with the NACK Reception in Master Mode ......773 22.15.6 Notes on the RDRF Flag Set Timing Selection Bit (RDRFS) ............... 773 23. A/D Converter ............................774 23.1 Overview ................................. 774 23.2 Register Descriptions ............................781 23.2.1 A/D Data Register y (ADDRy) (y = A to D) ..................
Page 24 24.2.3 DADRy Format Select Register (DADPR) .................... 813 24.3 Operation ................................. 814 24.4 Usage Notes ..............................815 24.4.1 Module Stop Function Setting........................ 815 24.4.2 Operation of the D/A Converter in Module Stop State ................815 24.4.3 Operation of the D/A Converter in Software Standby Mode ..............815 24.4.4 Note on Entering Deep Software Standby Mode ...................
Page 25 26.6.3 Connections between FCU Modes and Commands ................850 26.6.4 FCU Command Usage ........................... 851 26.6.4.1 Mode Transitions ..........................851 26.6.4.2 Programming and Erasure Procedures ....................855 26.6.4.3 Error Processing ..........................864 26.6.4.4 Suspension and Resumption ......................865 26.7 Suspending Operation ............................. 868 26.7.1 Suspension during Programming ......................
Page 26 27.6.1 FCU Modes ............................923 27.6.1.1 ROM P/E Modes ..........................924 27.6.1.2 ROM/Data Flash Read Mode ......................924 27.6.1.3 Data Flash P/E Modes ........................924 27.6.2 FCU Commands ............................. 925 27.6.3 Connections between FCU Modes and Commands ................926 27.6.4 FCU Command Usage ...........................
Page 27 Appendix 1. Port States in Each Processing Mode ..................980 Appendix 2. Package Dimensions ....................... 985 REVISION HISTORY ............................987...
Page 28: Overview
Overview Features The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core. One basic instruction is executable in one cycle of the system clock. Calculation functionality is further enhanced, with the inclusion of a single-precision floating-point calculation unit as well as a 32-bit multiplier and divider. Additionally, code efficiency is improved by instructions with lengths that are variable in byte units and by an enhanced range of addressing modes.
Page 29: Outline Of Specifications
RX610 Group 1. Overview 1.1.2 Outline of Specifications Table 1.1 lists the specifications of the RX610 Group in outline. Table 1.1 Outline of Specifications Classification Module/Function Description • Maximum operating frequency: 100 MHz • 32-bit RX CPU • Minimum instruction execution time: One instruction in one state (in one system clock cycle) •...
Page 30 RX610 Group 1. Overview Classification Module/Function Description • Interrupt Interrupt control unit Peripheral function interrupts: 116 • External interrupts: 16 (pins IRQ15 to IRQ0) • Non-maskable interrupt: 1 (the NMI pin) • Eight priority orders specifiable • External bus extension The external address space can be divided into eight areas (CS0 to CS7), each of which is independently controllable.
Page 31 RX610 Group 1. Overview • Watchdog timer 8 bits x 1 channel • Select from among 8 counter-input clocks • Switchable between watchdog timer mode and interval timer mode • Communication Serial communication 7 channels • function interface Serial communication mode: Asynchronous, clock synchronous, and smart card interface •...
Page 32: List Of Products
RX610 Group 1. Overview List of Products Table 1.2 is the list of products, and figure 1.1 shows how to read the product part no. Table 1.2 List of Products Operating Part No. Package ROM Capacity RAM Capacity Data Flash Frequency (Max.) R5F56108VNFP PLQP0144KA-A...
Page 33 7: 1.5 Mbytes/128 Kbytes/32 Kbytes 6: 1 Mbyte/128 Kbytes/32 Kbytes 4: 768 Kbytes/128 Kbytes/32 Kbytes Indicates the RX610 Group. Indicates the RX600 Series. Indicates the type of memory. F: Flash memory version Indicates a Renesas MCU. Indicates a Renesas semiconductor product.
Page 34: Block Diagram
RX610 Group 1. Overview Block Diagram Figure 1.2 shows a block diagram of the RX610 Group. Data flash Port 0 Port 1 Port 2 SCI × 7 channels Port 3 TPU × 6 channels (unit 0) Port 4 TPU × 6 channels (unit 1) Port 5 PPG (unit 0) PPG (unit 1)
Page 35: Pin Assignments
RX610 Group 1. Overview Pin Assignments Figures 1.3 and 1.4 show the pin assignments of the 176-pin LFBGA and the 144-pin LQFP, respectively. Figure 1.5 (assistance diagram) shows the pin assignment the 144-pin LQFP. Tables 1.3 and 1.4 show the lists of pins and pin functions of the 176-pin LFBGA and the 144-pin LQFP, respectively.
Page 36 RX610 Group 1. Overview PE0/D8 PC4/A20 PD7/D7 PC5/A21/SCK5/CS5#-D PD6/D6 PC6/A22/RxD5/CS6#-D PD5/D5 PC7/A23/TxD5/CS4#-D/CS7#-D PD4/D4 P64/CS4#-B P76/IRQ14-A P63/CS3#-A/CS7#-A P62/CS2#-A/CS6#-A P50/WR0#/WR# P61/CS1#/CS2#-B/CS5#-A/CS6#-B/CS7#-B P51/WR1#/BC1# P60/CS0#/CS4#-A/CS5#-B P52/RD# PD3/D3 P53/BCLK PD2/D2 PD1/D1 P81/TRSYNC PD0/D0 P97/AN15 P82/TRCLK RX610 Group P96/AN14 P95/AN13 PLQP0144KA-A P94/AN12 P54/TRDATA0 （144-pin LQFP） P93/AN11 P55/TRDATA1 P92/AN10 P56/TRDATA2...
Page 37 RX610 Group 1. Overview PC4/A20 PC5/A21/SCK5/CS5#-D PC6/A22/RxD5/CS6#-D PC7/A23/TxD5/CS4#-D/CS7#-D P76/IRQ14-A P50/WR0#/WR# P51/WR1#/BC1# P52/RD# PE0/D8 P53/BCLK PD7/D7 PD6/D6 P81/TRSYNC PD5/D5 PD4/D4 P82/TRCLK P64/CS4#-B P63/CS3#-A/CS7#-A P62/CS2#-A/CS6#-A P54/TRDATA0 P61/CS1#/CS2#-B/CS5#-A/CS6#-B/CS7#-B P55/TRDATA1 P60/CS0#/CS4#-A/CS5#-B P56/TRDATA2 PD3/D3 RX610 Group P57/WAIT#/TRDATA3 PD2/D2 PLQP0144KA-A PD1/D1 P35/PO13/TIOCA1/TIOCB1/TCLKC-A PD0/D0 （144-pin LQFP） P36/PO14/TIOCA2 P97/AN15 （Top view）...
Page 38 RX610 Group 1. Overview Table 1.3 List of Pins and Pin Functions (176-Pin LFBGA) Pin No. Power Supply 176-Pin Clock External Communi- On-Chip LFBGA System Control I/O Port Interrupt Timer cation Analog Emulator IRQ12-A TMCI3 TxD4 AVCC VREFL IRQ11-B IRQ14-B AN11 AN15 CS0#/...
Page 39 RX610 Group 1. Overview Pin No. Power Supply 176-Pin Clock External Communi- On-Chip LFBGA System Control I/O Port Interrupt Timer cation Analog Emulator AN12 BSCANP CS2#-A/ CS6#-A IRQ5-A IRQ15-A IRQ9-A TMCI2 RxD6 AVSS IRQ8-B IRQ12-B AN13 CS4#-B IRQ6-A IRQ7-A WDTOVF# EMLE IRQ8-A TMRI2...
Page 40 RX610 Group 1. Overview Pin No. Power Supply 176-Pin Clock External Communi- On-Chip LFBGA System Control I/O Port Interrupt Timer cation Analog Emulator PO18/ TIOCC6/ TCLKE A0/BC0# PO16/ TIOCA6 PO17/ TIOCA6/ TIOCB6 RES# XTAL PO23/ TIOCA8/ TIOCB8/ TCLKH PO22/ TIOCA8 PO20/ TIOCA7 PO21/...
Page 41 RX610 Group 1. Overview Pin No. Power Supply 176-Pin Clock External Communi- On-Chip LFBGA System Control I/O Port Interrupt Timer cation Analog Emulator CS3#-B ADTRG2# IRQ1-A PO9/ TIOCA0/ TIOCB0 IRQ0-A PO8/ TIOCA0 IRQ2-A PO10/ TIOCC0/ TCLKA-A IRQ3-A PO11/ TIOCC0/ TIOCD0/ TCLKB-A PO26/ TIOCC9...
Page 42 RX610 Group 1. Overview Pin No. Power Supply 176-Pin Clock External Communi- On-Chip LFBGA System Control I/O Port Interrupt Timer cation Analog Emulator PO15/ TIOCA2/ TIOCB2/ TCLKD-A WAIT# TRDATA3 TRSYNC WR1#/BC1# A23/ TxD5 CS4#-D/ CS7#-D PO30/ TIOCA11 PO5/ RxD1 TIOCA4/ TMCI1 PO4/ TIOCA4/...
Page 43 RX610 Group 1. Overview Pin No. Power Supply 176-Pin Clock External Communi- On-Chip LFBGA System Control I/O Port Interrupt Timer cation Analog Emulator PO2/ SCK0 TIOCC3/ TMO0 PLLVCC IRQ5-B TCLKB-B SCK3/SCL1 IRQ1-B SCK2 TRDATA0 A22/ RxD5 CS6#-D PO1/ RxD0 TIOCA3/ TMCI0 IRQ7-B TCLKD-B...
Page 44 RX610 Group 1. Overview Table 1.4 List of Pins and Pin Functions (144-Pin LQFP) Pin No. Power Supply 144-Pin Clock External Communi- On-Chip LQFP System Control I/O Port Interrupt Timer cation Analog Emulator IRQ12-A TMCI3 TxD4 IRQ11-A TMRI3 SCK4 AVSS IRQ10-A TMO2 SCK6...
Page 45 RX610 Group 1. Overview Pin No. Power Supply 144-Pin Clock External Communi- On-Chip LQFP System Control I/O Port Interrupt Timer cation Analog Emulator PO5/ RxD1 TIOCA4/ TMCI1 PO4/ TIOCA4/ TIOCB4/ TMRI1 PO3/ TIOCC3/ TIOCD3 PO2/ SCK0 TIOCC3/ TMO0 PO1/ RxD0 TIOCA3/ TMCI0 PO0/...
Page 46 RX610 Group 1. Overview Pin No. Power Supply 144-Pin Clock External Communi- On-Chip LQFP System Control I/O Port Interrupt Timer cation Analog Emulator TRDATA0 TRCLK TRSYNC# BCLK WR1#/BC1# WR0#/WR# IRQ14-A A23/ TxD5 CS4#-D/ CS7#-D A22/ RxD5 CS6#-D A21/ SCK5 CS5#-D PO31/ TIOCA11/ TIOCB11...
Page 47 RX610 Group 1. Overview Pin No. Power Supply 144-Pin Clock External Communi- On-Chip LQFP System Control I/O Port Interrupt Timer cation Analog Emulator PO25/ TIOCA9/ TIOCB9 ADTRG3# CS4#-C/ CS5#-C/ CS6#-C/ CS7#-C CS3#-B ADTRG2# PO24/ TIOCA9 PO23/ TIOCA8/ TIOCB8/ TCLKH PO22/ TIOCA8 PO21/ TIOCA7/...
Page 48 RX610 Group 1. Overview Pin No. Power Supply 144-Pin Clock External Communi- On-Chip LQFP System Control I/O Port Interrupt Timer cation Analog Emulator CS4#-B CS3#-A/ CS7#-A CS2#-A/ CS6#-A CS1#/ CS2#-B/ CS5#-A/ CS6#-B/ CS7#-B CS0#/ CS4#-A/ CS5#-B AN15 AN14 AN13 AN12 AN11 AN10 IRQ15-B...
Page 49: Pin Functions
RX610 Group 1. Overview Pin Functions Table 1.5 lists the pin functions. Table 1.5 Pin Functions Classifications Pin Name Description Power supply Input Power supply pin. Connect it to the system power supply. Input Connect this pin to VSS via a 0.1-µF capacitor. The capacitor should be placed close to the pin.
Page 50 RX610 Group 1. Overview Classifications Pin Name Description Bus control Output Strobe signal which indicates that reading from the external address space is in progress. WR0# Output Strobe signal which indicates that the lower-order byte (D0 to D7) is valid in writing to the external address space, in byte strobe mode.
Page 51 RX610 Group 1. Overview Classifications Pin Name Description Interrupt Input Non-maskable interrupt request signal IRQ0-A/IRQ0-B Input Maskable request signals IRQ1-A/IRQ1-B IRQ2-A/IRQ2-B IRQ3-A/IRQ3-B IRQ4-A/IRQ4-B IRQ5-A/IRQ5-B IRQ6-A/IRQ6-B IRQ7-A/IRQ7-B IRQ8-A/IRQ8-B IRQ9-A/IRQ9-B IRQ10-A/IRQ10-B IRQ11-A/IRQ11-B IRQ12-A/IRQ12-B IRQ13-A/IRQ13-B IRQ14-A/IRQ14-B IRQ15-A/IRQ15-B 16-bit timer pulse unit TIOCA0, TIOCB0 Signals for TGRA0 to TGRD0.
Page 52 RX610 Group 1. Overview Classifications Pin Name Description 16-bit timer pulse unit TCLKA-A/TCLKA-B Input Input pins for external clock signals TCLKB-A/TCLKB-B TCLKC-A/TCLKC-B TCLKD-A/TCLKD-B TCLKE, TCLKF TCLKG, TCLKH Programmable pulse PO0 to PO31 Output Output pins for the pulse signals generator 8-bit timer TMO0 to TMO3 Output...
Page 53 RX610 Group 1. Overview Classifications Pin Name Description Analog power supply AVCC Input Analog power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. AVSS Input Ground pin for the A/D and D/A converters.
Page 54: Cpu
RX610 Group 2. CPU The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core. A variable-length instruction format has been adopted for the RX CPU. Allocating the more frequently used instructions to the shorter instruction lengths facilitates the development of efficient programs that take up less memory. The CPU has 73 basic instructions and 8 floating-point operation instructions, and 9 DSP instructions, for a total of 90 instructions.
Page 55: Register Set Of The Cpu
RX610 Group 2. CPU Register Set of the CPU The RX CPU has sixteen general-purpose registers, nine control registers, and one accumulator used for DSP instructions. General-purpose register R0 (SP) * Control register (Interrupt stack pointer) (User stack pointer) INTB (Interrupt table register) (Program counter) (Processor status word)
Page 56: General-Purpose Registers (R0 To R15)
RX610 Group 2. CPU 2.2.1 General-Purpose Registers (R0 to R15) This CPU has sixteen general-purpose registers (R0 to R15). R1 to R15 can be used as data registers or address registers. R0, a general-purpose register, also functions as the stack pointer (SP). The stack pointer is switched to operate as the interrupt stack pointer (ISP) or user stack pointer (USP) by the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 57: Interrupt Stack Pointer (Isp)/User Stack Pointer (Usp)
RX610 Group 2. CPU 2.2.2.1 Interrupt Stack Pointer (ISP)/User Stack Pointer (USP) Value after reset: Value after reset: The stack pointer (SP) can be either of two types, the interrupt stack pointer (ISP) or the user stack pointer (USP). Whether the stack pointer operates as the ISP or USP depends on the value of the stack pointer select bit (U) in the processor status word (PSW).
Page 58: Processor Status Word (Psw)
RX610 Group 2. CPU 2.2.2.4 Processor Status Word (PSW) IPL[2:0] * Value after reset: Value after reset: Note: * The MVTIPL instruction is not supported in the RX610 Group. When writing to PSW.IPL[2:0], use the MVTC instruction. Symbol Bit Name Description 0: No carry has occurred.
Page 59 RX610 Group 2. CPU Notes: 1. In user mode, writing to the IPL[2:0], PM, U, and I bits by an MVTC or a POPC instruction is ignored. 2. In supervisor mode, writing to the PM bit by an MVTC or a POPC instruction is ignored, but writing to the other bits is possible.
Page 60: Backup Pc (Bpc)
RX610 Group 2. CPU 2.2.2.5 Backup PC (BPC) Value after reset: Undefined The backup PC (BPC) is provided to speed up response to interrupts. After a fast interrupt has been generated, the contents of the program counter (PC) are saved in the BPC. 2.2.2.6 Backup PSW (BPSW) Value after reset: Undefined...
Page 61: Floating-Point Status Word (Fpsw)
RX610 Group 2. CPU 2.2.2.8 Floating-Point Status Word (FPSW) Value after reset: RM[1 0] Value after reset: Symbol Bit Name Description b1, b0 RM[1:0] Floating-Point Rounding-Mode Setting b1 b0 0 0: Rounding to the nearest value 0 1: Rounding to 0 ∞...
Page 62 RX610 Group 2. CPU Symbol Bit Name Description Invalid Operation Flag 0: No invalid operation has been encountered. 1: Invalid operation has been encountered.* Overflow Flag 0: No overflow has occurred. 1: Overflow has occurred.* Division-by-Zero Flag 0: No division-by-zero has occurred. 1: Division-by-zero has occurred.* Underflow Flag 0: No underflow has occurred.
Page 63 RX610 Group 2. CPU Explanation of Floating-Point Rounding Modes An inexact result is rounded to the available value that is • Rounding to the nearest value (the default behavior): closest to the result which would be obtained with an infinite number of digits.
Page 64: Accumulator (Acc)
RX610 Group 2. CPU FV Flag (Invalid Operation flag), FO Flag (Overflow Flag), FZ Flag (Division-by-Zero Flag), FU Flag (Underflow Flag), and FX Flag (Inexact Flag) While the exception handling enable bit (Ej) is 0 (exception handling is masked), if any of five floating-point exceptions specified in the IEEE754 standard is generated, the corresponding bit is set to 1.
Page 65: Processor Mode
RX610 Group 2. CPU Processor Mode The RX CPU supports two processor modes, supervisor and user. These processor modes enable the realization of a hierarchical CPU resource protection. Each processor mode imposes a level on rights of access to the CPU resource and the instructions that can be executed. Supervisor mode carries greater rights than those of user mode.
Page 66: Data Types
RX610 Group 2. CPU Data Types The RX CPU can handle four types of data: integer, floating-point, bit, and string. 2.4.1 Integer An integer can be signed or unsigned. For signed integers, negative values are represented by two's complements. Signed byte (8-bit) integer Unsigned byte (8-bit) integer Signed word (16-bit) integer Unsigned word (16-bit) integer...
Page 67: Bitwise Operations
RX610 Group 2. CPU The floating-point format supports the values listed below. • 0 < E < 255 (normal numbers) • E = 0 and F = 0 (signed zero) • E = 0 and F > 0 (denormalized numbers) Note: The number is treated as 0 when the DN bit in the FPSW is 1.
Page 68: Endian
RX610 Group 2. CPU Endian For the RX CPU, instructions are always little endian, but the treatment of data is selectable as little or big endian. 2.5.1 Switching the Endian As arrangements of bytes, the RX610 Group supports both big endian, where the higher-order byte (MSB) is at location 0, and little endian, where the lower-order byte (LSB) is at location 0.
Page 69 RX610 Group 2. CPU Table 2.2 32-Bit Read Operations when Big Endian has been Selected Operation Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Reading a 32-bit unit Address of src from address 0 from address 1 from address 2 from address 3...
Page 70 RX610 Group 2. CPU Table 2.5 16-Bit Read Operations when Little Endian has been Selected Operation Reading a 16-bit Reading a 16-bit Reading a 16-bit Reading a 16-bit Reading a 16-bit Reading a 16-bit Reading a 16-bit unit from unit from unit from unit from unit from...
Page 71 RX610 Group 2. CPU Table 2.8 16-Bit Write Operations when Big Endian has been Selected Writing a 16-bit Writing a 16-bit Writing a 16-bit Writing a 16-bit Writing a 16-bit Writing a 16-bit Writing a 16-bit Operation unit to address 0 unit to address 1 unit to address 2 unit to address 3...
Page 72: Access To I/O Registers
RX610 Group 2. CPU Table 2.12 8-Bit Write Operations when Big Endian has been Selected Operation Writing an 8-bit unit to Writing an 8-bit unit to Writing an 8-bit unit to Writing an 8-bit unit to Address of dest address 0 address 1 address 2 address 3...
Page 73: Data Arrangement
RX610 Group 2. CPU 2.5.4 Data Arrangement 2.5.4.1 Data Arrangement in Registers Figure 2.6 shows the relation between the sizes of registers and bit numbers. Byte (8-bit) data Word (16-bit) data Longword (32-bit) data Figure 2.6 Data Arrangement in Registers 2.5.4.2 Data Arrangement in Memory Data in memory have three sizes: byte (8-bit), word (16-bit), and longword (32-bit).
Page 74: Vector Table
RX610 Group 2. CPU Vector Table There are two types of vector table: fixed and relocatable. Each vector in the vector table consists of four bytes and specifies the address where the corresponding exception processing routine starts. 2.6.1 Fixed Vector Table The fixed vector table is allocated to a fixed address range.
Page 75: Relocatable Vector Table
RX610 Group 2. CPU 2.6.2 Relocatable Vector Table The address where the relocatable vector table is placed can be adjusted. The table is a 1,024-byte region that contains all vectors for unconditional traps and interrupts and starts at the address (IntBase) specified in the interrupt table register (INTB).
Page 76: Operation Of Instructions
RX610 Group 2. CPU Operation of Instructions 2.7.1 Data Prefetching by the RMPA Instruction and the String-Manipulation Instructions The RMPA instruction and the string-manipulation instructions (SCMPU, SMOVB, SMOVF, SMOVU, SUNTIL, SWHILE, and SSTR instructions are not included) may prefetch data from the memory to speed up the read processing. Data is prefetched from the prefetching start position with three bytes as the upper limit.
Page 77: Pipeline
RX610 Group 2. CPU Pipeline 2.8.1 Overview The RX CPU has 5-stage pipeline structure. The RX CPU instruction is converted into one or more micro-operations, which are then executed in pipeline processing. In the pipeline stage, the IF stage is executed in the unit of instructions, while the D and subsequent stages are executed in the unit of micro-operations.
Page 78 RX610 Group 2. CPU Figure 2.10 shows the pipeline configuration and its operation. One cycle M stage IF stage D stage E stage M1 stage M2 stage WB stage Pipeline stage Execution processing Figure 2.10 Pipeline Configuration and its Operation R01UH0032EJ0120 Rev.1.20 Page 78 of 1006 Feb 20, 2013...
Page 79: Instructions And Pipeline Processing
RX610 Group 2. CPU 2.8.2 Instructions and Pipeline Processing The operands in the table below indicate the following meaning. #IMM: Immediate Rs, Rs2, Rd, Rd2, Ri, Rb: General-purpose register, CR: Control register dsp: dsp5, dsp8, dsp16, dsp24 pcdsp: pcdsp3, pcdsp8, pcdsp16, pcdsp24 2.8.2.1 Instructions Converted into Single Micro-Operation and Pipeline Processing The table below lists the instructions that are converted into a single micro-operation.
Page 80 RX610 Group 2. CPU Figures 2.11 to 2.13 show the operation of instructions that are converted into a basic single micro-operation. 4 stages Note: Multi-cycle instructions (DIV, DIVU) are executed in multiple cycles in the E stage. Figure 2.11 Operation for Register-Register, Immediate-Register 5 stages Note: When the load operation is executed to the no-wait memory, the M1 stage is executed in one cycle.
Page 81: Instructions Converted Into Multiple Micro-Operations And Pipeline Processing
RX610 Group 2. CPU 2.8.2.2 Instructions Converted into Multiple Micro-Operations and Pipeline Processing The table below lists the instructions that are converted into multiple micro-operations. The number of cycles in the table indicates the number of cycles during no-wait memory access. Table 2.14 Instructions that are Converted into Multiple Micro-Operations Mnemonic (indicates the common...
Page 82 RX610 Group 2. CPU Mnemonic (indicates the common Reference Instruction operation when the size is omitted) Figure Number of Cycles  • 2+4×floor(n/4)+4×(n%4) String manipulation instructions* SCMPU n: Number of comparison bytes*  • n>3? SMOVB 6+3×floor(n/4)+3×(n%4): 2+3n n: Number of transfer bytes* ...
Page 83 RX610 Group 2. CPU Figures 2.14 to 2.19 show the operation of instructions that are converted into basic multiple micro-operations. Small letters in figures below indicate micro-operations. [Legend] mop: Micro-operation, stall: Pipeline stall Bypass process ADD [R1], R2 (mop1) load stall (mop2) add Figure 2.14...
Page 84: Pipeline Basic Operation
RX610 Group 2. CPU 2.8.2.3 Pipeline Basic Operation In the ideal pipeline processing, each stage is executed in one cycle, though all instructions may not be pipelined in due to the processing and the branch execution. The CPU controls the pipeline stage with the IF stage in the unit of instructions, while the D and subsequent stages in the unit of micro-operations.
Page 85 RX610 Group 2. CPU MOV [R2], R1 (mop) load Bypass process ADD R2, R1 (mop) add stall Figure 2.23 When the Subsequent Instruction Uses an Operand Read from the Memory Pipeline Flow with no Stall Bypass process Even when the result of the preceding instruction will be used in a subsequent instruction, the operation processing between registers is pipelined in by the bypass process.
Page 86: Calculation Of The Instruction Processing Time
RX610 Group 2. CPU When subsequent instruction writes to the same register before the end of memory load Even when the subsequent instruction writes to the same register before the end of memory load, the operation processing is pipelined in, because the WB stage for the memory load is canceled. ×...
Page 87: Numbers Of Cycles For Response To Interrupts
RX610 Group 2. CPU 2.8.4 Numbers of Cycles for Response to Interrupts Table 2.15 lists numbers of cycles taken by processing for response to interrupts. Table 2.15 Numbers of Cycles for Response to Interrupts Type of Interrupt Request/Details of Processing Fast Interrupt Other Interrupts 2 cycles...
Page 88: Operating Modes
RX610 Group 3. Operating Modes Operating Modes Operating Mode Types and Selection Operating modes are specified by the MD1 and MD0 pins and the ROME and EXBE bits in the system control register 0 (SYSCR0). The endian can be selected in each operating mode. Endian is specified by the MDE pin. For details on the endian, see section 11, Buses.
Page 89: Register Descriptions
RX610 Group 3. Operating Modes Register Descriptions Table 3.4 lists the registers related to operating modes. Table 3.4 Registers Related to Operating Modes Register Name Symbol Value after Reset Address Access Size Mode monitor register MDMONR 10000000 x00000xxb 0008 0000h Mode status register MDSR 00000000 00001001b...
Page 90: Mode Status Register (Mdsr)
RX610 Group 3. Operating Modes 3.2.2 Mode Status Register (MDSR) Address: 0008 0002h — — — — — — — — Value after reset: — — UBTS BOTS BSW[1:0] IROM Value after reset: Symbol Bit Name Description IROM On-Chip ROM Startup Status Flag 0: The on-chip ROM is disabled at startup 1: The on-chip ROM is enabled at startup External Bus Startup Status Flag...
Page 91: System Control Register 0 (Syscr0)
RX610 Group 3. Operating Modes 3.2.3 System Control Register 0 (SYSCR0) Address: 0008 0006h KEY[7:0] Value after reset: — — — — — — EXBE ROME Value after reset: Symbol Bit Name Description ROME On-Chip FLASH Enable 0: The on-chip FLASH is disabled 1: The on-chip ROM is enabled EXBE External Bus Enable...
Page 92 RX610 Group 3. Operating Modes KEY[7:0] Bits (SYSCR0 Key Code) The KEY[7:0] bits enable or disable modifying SYSCR0. When writing a value to the ROME or EXBE bit, write 5Ah to the KEY[7:0] bits simultaneously. If SYSCR0 is modified with a KEY[7:0] value other than 5Ah, the ROME and EXBE values remain unchanged. R01UH0032EJ0120 Rev.1.20 Page 92 of 1006 Feb 20, 2013...
Page 93: System Control Register 1 (Syscr1)
RX610 Group 3. Operating Modes 3.2.4 System Control Register 1 (SYSCR1) Address: 0008 0008h — — — — — — — — Value after reset: — — — — — — — RAME Value after reset: Symbol Bit Name Description RAME RAM Enable 0: The on-chip RAM is disabled...
Page 94: Details Of Operating Modes
RX610 Group 3. Operating Modes Details of Operating Modes 3.3.1 Single-Chip Mode In this mode, the on-chip ROM is enabled or disabled, the external bus is disabled (EXBE bit = 0 in SYSCR0), and all I/O ports can be used as input/output ports. The on-chip ROM is enabled when this LSI is started.
Page 95: Transitions Of Operating Modes
RX610 Group 3. Operating Modes Transitions of Operating Modes 3.4.1 Operating Mode Transitions According to Mode Pin Setting Figure 3.1 shows operating mode transitions according to the setting of pins MD1 and MD0. Operating modes can shift in the direction of arrow. Reset state RES# = 0 RES# = 0...
Page 96: Operating Mode Transitions According To Register Setting
RX610 Group 3. Operating Modes 3.4.2 Operating Mode Transitions According to Register Setting Figure 3.2 shows operating mode transitions according to the setting of the ROME and EXBE bits in SYSCR0. Operating modes can shift in the direction of arrow. Single-chip mode User boot mode On-chip ROM enabled extended...
Page 97: Address Space
RX610 Group 4. Address Space Address Space Address Space This MCU has a 4-Gbyte address space, consisting of the range of addresses from 0000 0000h to FFFF FFFFh. That is, linear access to an address space of up to 4 Gbytes is possible, and this contains both program and data areas. Figures 4.1 to 4.4 show the memory maps in the respective operating modes of each product.
Page 98 RX610 Group 4. Address Space On-chip ROM enabled On-chip ROM disabled Single-chip mode* extended mode extended mode 0000 0000h 0000 0000h 0000 0000h On-chip RAM On-chip RAM On-chip RAM 0002 0000h 0002 0000h 0002 0000h Reserved area* Reserved area* Reserved area* 0008 0000h 0008 0000h 0008 0000h...
Page 99 RX610 Group 4. Address Space On-chip ROM enabled On-chip ROM disabled Single-chip mode* extended mode extended mode 0000 0000h 0000 0000h 0000 0000h On-chip RAM On-chip RAM On-chip RAM 0002 0000h 0002 0000h 0002 0000h Reserved area* Reserved area* Reserved area* 0008 0000h 0008 0000h 0008 0000h...
Page 100 RX610 Group 4. Address Space On-chip ROM enabled On-chip ROM disabled Single-chip mode* extended mode extended mode 0000 0000h 0000 0000h 0000 0000h On-chip RAM On-chip RAM On-chip RAM 0002 0000h 0002 0000h 0002 0000h Reserved area* Reserved area* Reserved area* 0008 0000h 0008 0000h 0008 0000h...
Page 101: External Address Space
RX610 Group 4. Address Space External Address Space The external address space is divided into up to 8 areas, each corresponding to the CSi# signal output from a CSi# (i = 0 to 7) pin. Figure 4.5 shows the address ranges corresponding to the individual CSi# signals (CSi areas, i = 0 to 7) in on-chip ROM disabled external extended mode.
Page 102: I/O Registers
RX610 Group 5. I/O Registers I/O Registers This section gives information on the on-chip I/O register addresses and bit configurations. The information is given as shown below. Notes on writing to registers are also given at the end. I/O register addresses (address order) •...
Page 103 RX610 Group 5. I/O Registers [Instruction examples] • Byte-size I/O registers MOV.L #SFR_ADDR, R1 MOV.B #SFR_DATA, [R1] [R1].UB, R1 ;; Next process • Word-size I/O registers MOV.L #SFR_ADDR, R1 MOV.W #SFR_DATA, [R1] [R1].W, R1 ;; Next process • Longword-size I/O registers MOV.L #SFR_ADDR, R1 MOV.L...
Page 104: I/O Register Addresses (Address Order)
RX610 Group 5. I/O Registers I/O Register Addresses (Address Order) Table 5.1 List of I/O Registers (Address Order) Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 0000h SYSTEM Mode monitor register MDMONR 3 ICLK 0008 0002h...
Page 105 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 2400h DMAC0 DMA control register A DMCRA 3 ICLK 0008 2404h DMAC0 DMA control register B DMCRB 3 ICLK 0008 2405h DMAC0 DMA control register C...
Page 106 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 3072h CS7 mode register CS7MOD 1 to 2 BCLK 0008 3074h CS7 wait control register 1 CS7WCNT1 1 to 2 BCLK 0008 3078h CS7 wait control register 2 CS7WCNT2...
Page 107 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 7064h Interrupt request register 100 IR100 2 ICLK 0008 7065h Interrupt request register 101 IR101 2 ICLK 0008 7068h Interrupt request register 104 IR104 2 ICLK...
Page 108 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 70A0h Interrupt request register 160 IR160 2 ICLK 0008 70A1h Interrupt request register 161 IR161 2 ICLK 0008 70A2h Interrupt request register 162 IR162 2 ICLK...
Page 109 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 70EAh Interrupt request register 234 IR234 2 ICLK 0008 70EBh Interrupt request register 235 IR235 2 ICLK 0008 70ECh Interrupt request register 236 IR236 2 ICLK...
Page 110 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 7170h Interrupt request destination setting register 112 ISELR112 2 ICLK 0008 7175h Interrupt request destination setting register 117 ISELR117 2 ICLK 0008 7176h...
Page 111 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 71E3h Interrupt request destination setting register 227 ISELR227 2 ICLK 0008 71E4h Interrupt request destination setting register 228 ISELR228 2 ICLK 0008 71E7h...
Page 112 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 7321h Interrupt priority register 21 IPR21 2 ICLK 0008 7322h Interrupt priority register 22 IPR22 2 ICLK 0008 7323h Interrupt priority register 23 IPR23 2 ICLK...
Page 113 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 7369h Interrupt priority register 69 IPR69 2 ICLK 0008 736Ah Interrupt priority register 6A IPR6A 2 ICLK 0008 736Bh Interrupt priority register 6B IPR6B 2 ICLK...
Page 114 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 802Bh Reset control/status register RSTCSR 2 to 3 PCLK 0008 8040h A/D data register A ADDRA 2 to 3 PCLK 0008 8042h A/D data register B ADDRB...
Page 115 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 8116h TPU0 Timer counter TCNT 2 to 3 PCLK 0008 8118h TPU0 Timer general register A TGRA 2 to 3 PCLK 0008 811Ah TPU0 Timer general register B...
Page 116 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 8166h TPU5 Timer counter TCNT 2 to 3 PCLK 0008 8168h TPU5 Timer general register A TGRA 2 to 3 PCLK 0008 816Ah TPU5 Timer general register B...
Page 117 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 81C2h TPU10 Timer I/O control register TIOR 2 to 3 PCLK 0008 81C4h TPU10 Timer interrupt enable register TIER 2 to 3 PCLK 0008 81C5h...
Page 118 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 820Ah TMR0 Timer counter control register TCCR 8 or 16 2 to 3 PCLK 0008 820Bh TMR1 Timer counter control register TCCR 8 or 16 2 to 3 PCLK...
Page 119 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 825Fh SCI3 Serial extended mode register SEMR 2 to 3 PCLK 0008 8260h SCI4 Serial mode register SMR* 2 to 3 PCLK 0008 8261h SCI4...
Page 120 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 830Fh RIIC0 Slave address register U2 SARU2 2 to 3 PCLK 0008 8310h RIIC0 I2C bus bit rate low-level register ICBRL 2 to 3 PCLK 0008 8311h...
Page 121 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 C020h Data register 2 to 3 PCLK 0008 C021h Data register 2 to 3 PCLK 0008 C022h Data register 2 to 3 PCLK 0008 C023h Data register...
Page 122 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 C069h Input buffer control register 2 to 3 PCLK 0008 C06Ah Input buffer control register 2 to 3 PCLK 0008 C06Bh Input buffer control register 2 to 3 PCLK...
Page 123 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 C29Ch SYSTEM Deep standby backup register 12 DPSBKR12 4 to 5 PCLK 0008 C29Dh SYSTEM Deep standby backup register 13 DPSBKR13 4 to 5 PCLK 0008 C29Eh...
Page 124 RX610 Group 5. I/O Registers Number of Module Register Number Access Access Address Abbreviation Register Name Abbreviation of Bits Size Cycles 0008 C329h IRQ control register 9 IRQCR9 2 to 3 PCLK 0008 C32Ah IRQ control register 10 IRQCR10 2 to 3 PCLK 0008 C32Bh IRQ control register 11 IRQCR11...
Page 125: I/O Register Bits
RX610 Group 5. I/O Registers I/O Register Bits Register addresses and bit names of the peripheral modules are described below. Each line cover eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively. Table 5.2 List of I/O Registers (Bit Order) Module Register...
Page 126 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation     DMAC0 DMMOD OPSEL[3:0]      SZSEL[2:0]   SMOD[2:0] DMOD[2:0]       ...
Page 127 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation       DMAC3 DMCBC     DMAC3 DMMOD OPSEL[3:0]      SZSEL[2:0]   SMOD[2:0] DMOD[2:0] ...
Page 128 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation DMAC3 DMRSA DMAC3 DMRDA       DMAC3 DMRBC       DMAC0 DMCRA DSEL[1:0]   ...
Page 129 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation        Common to DMSCNT DMST all DMAC channels     Common to DMICNT DINTM0 DINTM1 DINTM2 DINTM3 all DMAC...
Page 130 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation    CS3WCNT1 CSRWAIT[4:0]    CSWWAIT[4 0]      CSPRWAIT[2:0]      CSPWWAIT[2:0]  ...
Page 131 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation   CS7WCNT2 CSON[2:0] WDON[2:0]   WRON[2:0] RDON[2:0]      WDOFF[2:0]   CSWOFF[2:0] CSROFF[2:0]     ...
Page 132 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation        IR066        IR067        IR068 ...
Page 133 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation        IR138        IR139        IR140 ...
Page 134 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation        IR217        IR218        IR219 ...
Page 135 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation       ISELR072 ISEL[1:0]       ISELR073 ISEL[1:0]       ISELR074 ISEL[1:0] ...
Page 136 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation       ISELR175 ISEL[1:0]       ISELR177 ISEL[1:0]       ISELR178 ISEL[1:0] ...
Page 137 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation IER17 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 IER18 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 IER19 IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1...
Page 138 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation      IPR54 IPR[2:0]      IPR55 IPR[2:0]      IPR56 IPR[2:0]   ...
Page 139 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation        SHORT DTCADMOD        DTCST DTCST      ...
Page 140 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation   ADCSR ADIE ADST CH[3:0]  ADCR TRGS[2:0] CKS[1:0] MODE[1:0]        ADDPR DPSEL ADSSTR ADDRA ADDRB ADDRC ADDRD ...
Page 141 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation        DADPR DPSEL   TSTRA CST5 CST4 CST3 CST2 CST1 CST0 (unit 0)   TSYRA SYNC5 SYNC4 SYNC3...
Page 142 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation TPU3 TIORH IOB[3:0] IOA[3:0] TPU3 TIORL IOD[3:0] IOC[3:0]   TPU3 TIER TTGE TCIEV TGIED TGIEC TGIEB TGIEA      ...
Page 143 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation         TPU6 TPU6 TCNT TPU6 TGRA TPU6 TGRB TPU6 TGRC TPU6 TGRD TPU7 CCLR[2:0] CKEG[1:0] TPSC[2:0] ...
Page 144 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation TPU9 TGRC TPU9 TGRD TPU10 CCLR[2:0] CKEG[1:0] TPSC[2:0]  TPU10 TMDR ICSELB   MD[3 0] TPU10 TIOR IOB[3:0] IOA[3:0]    TPU10 TIER TTGE...
Page 145 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation PPG1 PODRL POD23 POD22 POD21 POD20 POD19 POD18 POD17 POD16 PPG1 NDRH NDR31 NDR30 NDR29 NDR28 NDR27 NDR26 NDR25 NDR24 () () () () PPG1 NDRL...
Page 146 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation   SCI1 ORER TEND TDRE RDRF (TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) () () SCI1     SCI1 SCMR BCP2 SDIR SINV SMIF...
Page 147 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation     SCI5 SCMR BCP2 SDIR SINV SMIF       SCI5 SEMR ABCS ACS0  SCI6 STOP CKS[1:0] (GM) (BLK)
Page 148 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation RIIC1 ICMR2 DLCS SDDL[2:0] TMWE TMOH TMOL TMOS RIIC1 ICMR3 SMBS WAIT RDRFS ACKWP ACKBT ACKBR NF[1:0] RIIC1 ICFER FMPE SCLE NACKE SALE NALE MALE TMOE...
Page 149 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation     PORT PORT PORT PORT PORT PORT PORT PORT  PORT PORT PORT PORT PORT PORT PORT  PORT PORT PORT ...
Page 150 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation  I/O PORT PFCR0 CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E I/O PORT PFCR1 CS7S[1:0] CS6S[1:0] CS5S[1:0] CS4S[1:0]     ...
Page 151 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation SYSTEM DPSBKR17 BKUP177 BKUP176 BKUP175 BKUP174 BKUP173 BKUP172 BKUP171 BKUP170 SYSTEM DPSBKR18 BKUP187 BKUP186 BKUP185 BKUP184 BKUP183 BKUP182 BKUP181 BKUP180 SYSTEM DPSBKR19 BKUP197 BKUP196 BKUP195 BKUP194...
Page 152 RX610 Group 5. I/O Registers Module Register 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Abbreviation Abbreviation       IRQCR14 IRQMD[1:0]       IRQCR15 IRQMD[1:0] SSIER SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 SSI7...
Page 153 RX610 Group 5. I/O Registers When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address is 000881FDh. When different output triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 000881FFh and 000881FDh, respectively.
Page 154: Resets
RX610 Group 6. Resets Resets Overview There are three types of reset: pin reset, deep software standby reset, and watchdog timer reset. Table 6.1 lists the reset names and sources. Table 6.1 Reset Names and Sources Reset Name Source Pin reset The RES# pin input voltage is driven low.
Page 155 RX610 Group 6. Resets Table 6.2 Targets to be Initialized by Each Reset Type Reset Type Reset Target Pin Reset Deep Software Standby Reset Watchdog Timer Reset   Registers related to the power-down Reset function (RSTSR, DPSBYCR, DPSWCR, DPSIER, DPSIFR, DPSIEGR, FWEPROR) ...
Page 156: Register Descriptions
RX610 Group 6. Resets Register Descriptions Table 6.4 lists registers related to reset. Table 6.4 Registers Related to Reset Register Name Symbol Value after Reset Address Access Size Reset status register RSTSR 0008 C285h Reset control/status register RSTCSR 0008 802Bh 6.2.1 Reset Status Register (RSTSR) Address: 0008 C285h...
Page 157: Reset Control/Status Register (Rstcsr)
RX610 Group 6. Resets 6.2.2 Reset Control/Status Register (RSTCSR) Address: 0008 802Bh — — — — — — WOVF RSTE Value after reset: Symbol Bit Name Description b4 to b0  These bits are always read as 1. The write value should Reserved always be 1.
Page 158: Operation
RX610 Group 6. Resets Operation 6.3.1 Pin Reset This is a reset generated by the RES# pin. When the RES# pin is driven low, all the processing in progress is terminated and this LSI enters a reset state. To reset this LSI without fail, the specified oscillation settling time should be observed at power-on and then the RES# pin should be held low.
Page 159: Determining Reset Generation Source
RX610 Group 6. Resets Determining Reset Generation Source Reading RSTCSR and RSTSR allows the LSI to determine which reset was used to execute the reset exception handling. Figure 6.2 shows an example of flow to identify a reset generation source. Reset exception handling RSTCSR.RSTE = 1 &...
Page 160: Clock Generation Circuit
RX610 Group 7. Clock Generation Circuit Clock Generation Circuit Overview The RX610 Group has a clock generation circuit that generates the system clock (ICLK), peripheral module clock (PCLK), and external bus clock (BCLK). The clock generation circuit consists of a main clock oscillator, phase-locked loop (PLL) circuit, frequency divider, and selector circuit.
Page 161: Register Descriptions
RX610 Group 7. Clock Generation Circuit Table 7.2 lists the input/output pins of the clock generation circuit. Table 7.2 Pin Configuration Pin Name Description XTAL Input These pins are used to connect a crystal resonator. The EXTAL pin can also be used to input an external clock.
Page 162: System Clock Control Register (Sckcr)
RX610 Group 7. Clock Generation Circuit 7.2.1 System Clock Control Register (SCKCR) Address: 0008 0020h — — — — ICK[3:0] Value after reset: — — — PSTOP1 BCK[3:0] Value after reset: — — — — PCK[3:0] Value after reset: — —...
Page 163 RX610 Group 7. Clock Generation Circuit Notes: 1. Do not set a frequency higher than the system clock (ICLK). If such a frequency is set, the clock frequency will be the same as the ICLK. 2. Do not set a frequency lower than the peripheral module clock (PCLK) and external bus clock (BCLK). If such a frequency is set, the frequency of the PCLK and BCLK will change to the system clock (ICLK) frequency.
Page 164: Main Clock Oscillator
RX610 Group 7. Clock Generation Circuit Main Clock Oscillator Clock pulses can be supplied by connecting a crystal resonator or by inputting an external clock. 7.3.1 Connecting a Crystal Resonator Figure 7.2 shows an example of connecting a crystal resonator. Table 7.4 shows reference values of the damping resistance (Rd).
Page 165: External Clock Input
RX610 Group 7. Clock Generation Circuit 7.3.2 External Clock Input Figure 7.4 shows examples of external clock input. To leave the XTAL pin open, make the parasitic capacitance less than 10 pF. When the counter-phase clock is input to the XTAL pin, hold the external clock in high level during standby mode.
Page 166: Internal Clock
RX610 Group 7. Clock Generation Circuit Internal Clock The internal clock is generated by multiplying the external input clock (EXTAL) by 8 with the PLL circuit, and then by dividing the multiplied clock by 1, 2, 4, or 8 with the frequency divider. There are following three types of internal clock.
Page 167: Usage Notes
RX610 Group 7. Clock Generation Circuit Usage Notes 7.7.1 Notes on the Clock Generation Circuit The frequencies of the system clock (ICLK), peripheral module clock (PCLK), and external bus clock (BCLK) supplied to each module are selected according to the setting of SCKCR. Select each frequency that is within the operation guaranteed range of clock cycle time (tcyc) specified in AC characteristics of electrical characteristics.
Page 168: Notes On Resonator
RX610 Group 7. Clock Generation Circuit 7.7.2 Notes on Resonator Since various resonator characteristics relate closely to the user's board design, adequate evaluation is required on the user side before use, referencing the resonator connection example shown in this section. The circuit constants for the resonator depend on the resonator to be used and the stray capacitance of the mounting circuit.
Page 169: Low Power Consumption
RX610 Group 8. Low Power Consumption Low Power Consumption Overview The RX610 Group has functions to reduce power consumption, including a multi-clock function, BCLK output stop function, module stop function, and a function for transition to low power consumption mode. Table 8.1 lists the specifications of low power consumption.
Page 170 RX610 Group 8. Low Power Consumption Table 8.2 Transition and Cancellation of the Mode and the State of Operation Transition and Cancellation of the Mode and the State of All-Module Clock Stop Software Standby Deep Software Operation Sleep Mode Mode Mode Standby Mode Transition method...
Page 171 RX610 Group 8. Low Power Consumption SBYCR.SSBY = 0 Reset state WAIT instruction* Sleep mode RES# pin = High SBYCR.SSBY = 0 All interrupts MSTPCRA.ACSE = 1 MSTPCRA = FFFFFF[C-F]Fh MSTPCRB = FFFFFFFFh WAIT instruction* All-module clock stop mode Interrupt* Program execution state WAIT instruction* (DPSBYCR.DPSBY = 0 and...
Page 172: Register Descriptions
RX610 Group 8. Low Power Consumption Register Descriptions Table 8.3 is the list of low power consumption registers. For details on the system clock control register (SCKCR), see section 7.2.1, System Clock Control Register (SCKCR). Table 8.3 List of Low Power Consumption Registers Value after Register Name Symbol...
Page 173 RX610 Group 8. Low Power Consumption Value after Register Name Symbol Reset Address Access Size Deep standby backup register 29 DPSBKR29 xxh* 0008 C2ADh Deep standby backup register 30 DPSBKR30 xxh* 0008 C2AEh Deep standby backup register 31 DPSBKR31 xxh* 0008 C2AFh Note: * DPSBKR0 to DPSBKR31 are not initialized and their values are undefined immediately after power-on.
Page 174: Standby Control Register (Sbycr)
RX610 Group 8. Low Power Consumption 8.2.1 Standby Control Register (SBYCR) Address: 0008 000Ch SSBY — STS[4:0] Value after reset: — — — — — — — — Value after reset: Symbol Bit Name Description  b7 to b0 Reserved These bits are always read as 0.
Page 175 RX610 Group 8. Low Power Consumption STS[4:0] Bits (Standby Timer Select) These bits select the time for this LSI to wait until the clock is stabilized when software standby mode is canceled by an external interrupt. In the case of crystal oscillation, see table 8.4 and make a selection according to the operating frequency so that the waiting time is no less than the oscillation settling time.
Page 176: Module Stop Control Register A (Mstpcra)
RX610 Group 8. Low Power Consumption 8.2.2 Module Stop Control Register A (MSTPCRA) Address: 0008 0010h ACSE MSTPA28 MSTPA27 — — — — — Value after reset: MSTPA23 MSTPA22 MSTPA21 MSTPA20 MSTPA19 — — — Value after reset: MSTPA15 MSTPA14 MSTPA13 MSTPA12 MSTPA11 MSTPA10 —...
Page 177 RX610 Group 8. Low Power Consumption Symbol Bit Name Description MSTPA15 Compare Match Timer 0 (Unit 0) Target module: CMT unit 0 (CMT0, CMT1) Module Stop 0: The module stop state is canceled 1: Transition to the module stop state is made ...
Page 178: Module Stop Control Register B (Mstpcrb)
RX610 Group 8. Low Power Consumption 8.2.3 Module Stop Control Register B (MSTPCRB) Address: 0008 0014h MSTPB31 MSTPB30 MSTPB29 MSTPB28 MSTPB27 MSTPB26 MSTPB25 — Value after reset: MSTPB23 MSTPB21 MSTPB20 — — — — — Value after reset: — — —...
Page 179: Module Stop Control Register C (Mstpcrc)
RX610 Group 8. Low Power Consumption Symbol Bit Name Description MSTPB28 Serial Communication Interface 3 Target module: SCI3 Module Stop 0: The module stop state is canceled 1: Transition to the module stop state is made MSTPB29 Serial Communication Interface 2 Target module: SCI2 Module Stop 0: The module stop state is canceled...
Page 180 RX610 Group 8. Low Power Consumption 8.2.4 Module Stop Control Register C (MSTPCRC) Address: 0008 0018h — — — — — — — — Value after reset: — — — — — — — — Value after reset: — — —...
Page 181: Deep Standby Control Register (Dpsbycr)
RX610 Group 8. Low Power Consumption 8.2.5 Deep Standby Control Register (DPSBYCR) Address: 0008 C280h — — — DPSBY IOKEEP RAMCUT2 RAMCUT1 RAMCUT0 Value after reset: Symbol Bit Name Description RAMCUT0 On-Chip RAM Off 0 b5 b4 b0 0 0 0: Power is supplied to the on-chip RAM (RAM0*) in deep software standby mode 1 1 1: Power is not supplied to the on-chip RAM (RAM0*) in deep software standby mode...
Page 182: Deep Standby Wait Control Register (Dpswcr)
RX610 Group 8. Low Power Consumption IOKEEP Bit (I/O Port Retention) In deep software standby mode, I/O ports keep retaining the same states from software standby mode. The IOKEEP bit specifies whether to keep retaining the I/O port states from deep software standby mode even after deep software standby mode is canceled, or to cancel retaining the I/O port states.
Page 183: Deep Standby Interrupt Enable Register (Dpsier)
RX610 Group 8. Low Power Consumption 8.2.6 Deep Standby Wait Control Register (DPSWCR) Address: 0008 C281h — — WTSTS[5:0] Value after reset: Symbol Bit Name Description b5 to b0 WTSTS[5:0] Deep Software Standby Waiting Time 0 0 0 1 0 1: Waiting time = 64 states 0 0 0 1 1 0: Waiting time = 512 states 0 0 0 1 1 1: Waiting time = 1024 states 0 0 1 0 0 0: Waiting time = 2048 states...
Page 184: Deep Standby Interrupt Flag Register (Dpsifr)
RX610 Group 8. Low Power Consumption 8.2.7 Deep Standby Interrupt Enable Register (DPSIER) Address: 0008 C282h DNMIE — — — DIRQ3E DIRQ2E DIRQ1E DIRQ0E Value after reset: Symbol Bit Name Description DIRQ0E IRQ0 Pin Enable 0: Canceling deep software standby mode by the IRQ0 pin is disabled 1: Canceling deep software standby mode by the IRQ0 pin is enabled...
Page 185: Deep Standby Interrupt Edge Register (Dpsiegr)
RX610 Group 8. Low Power Consumption 8.2.8 Deep Standby Interrupt Flag Register (DPSIFR) Address: 0008 C283h DNMIF — — — DIRQ3F DIRQ2F DIRQ1F DIRQ0F Value after reset: Symbol Bit Name Description DIRQ0F IRQ0 Deep Standby Cancel Flag 0: No cancel request by the IRQ0 pin is generated R/(W)* 1: A cancel request by the IRQ0 pin is generated DIRQ1F...
Page 186: Reset Status Register (Rstsr)
RX610 Group 8. Low Power Consumption 8.2.9 Deep Standby Interrupt Edge Register (DPSIEGR) Address: 0008 C284h — — — DNMIEG DIRQ3EG DIRQ2EG DIRQ1EG DIRQ0EG Value after reset: Symbol Bit Name Description DIRQ0EG IRQ0 Edge Select 0: A cancel request is generated at a falling edge 1: A cancel request is generated at a rising edge DIRQ1EG IRQ1 Edge Select...
Page 187: Deep Standby Backup Register (Dpsbkry) (Y = 0 To 31)
RX610 Group 8. Low Power Consumption 8.2.10 Reset Status Register (RSTSR) Address: 0008 C285h DPSRSTF — — — — — — — Value after reset: Symbol Bit Name Description b6 to b0  Reserved These bits are always read as 0. The write value should always be 0.
Page 188: Multi-Clock Function
RX610 Group 8. Low Power Consumption Multi-Clock Function When the ICK[3:0], BCK[3:0], and PCK[3:0] bits in SCKCR are set, the clock frequency changes. The CPU and bus masters operate on the operating clock specified by the ICK[3:0] bits. Peripheral modules operate on the operating clock specified by the PCK[3:0] bits.
Page 189: Sleep Mode
RX610 Group 8. Low Power Consumption Low Power Consumption Modes 8.5.1 Sleep Mode 8.5.1.1 Transition to Sleep Mode When the WAIT instruction is executed while the SSBY bit in SBYCR is 0, the CPU enters sleep mode. In sleep mode, the CPU stops operating but the contents of its internal registers are retained. Other peripheral functions do not stop.
Page 190: Transitions To All-Module Clock Stop Mode
RX610 Group 8. Low Power Consumption 8.5.2 All-Module Clock Stop Mode 8.5.2.1 Transitions to All-Module Clock Stop Mode When the following two conditions are satisfied, executing the WAIT instruction with the SSBY bit in SBYCR cleared to 0 will cause the transition to all-module clock stop mode at the end of the bus cycle.* •...
Page 191 RX610 Group 8. Low Power Consumption 8.5.2.2 Release from All-Module Clock Stop Mode Release from all-module clock stop mode is triggered by an external interrupt (the NMI pin or any pin from among IRQ0 to IRQ15), the signal on the RES# pin, or an internal interrupt (from an 8-bit timer* or the watchdog timer), and normal program execution resumes once handling of the given exception is complete.
Page 192: Software Standby Mode
RX610 Group 8. Low Power Consumption 8.5.3 Software Standby Mode 8.5.3.1 Transition to Software Standby Mode When the WAIT instruction is executed with the SSBY bit in SBYCR set to 1 and the DPSBY bit in DPSBYCR cleared to 0, a transition to software standby mode is made. In this mode, the CPU, on-chip peripheral functions, and all the oscillator functions stop.
Page 193: Setting Oscillation Settling Time After Software Standby Mode Is Canceled
RX610 Group 8. Low Power Consumption 8.5.3.2 Canceling Software Standby Mode Software standby mode is canceled by an external interrupt (NMI or IRQ0 to IRQ15* ) or the reset signal from the RES# pin. 1. Canceling by an interrupt When an NMI or IRQ0 to IRQ15* interrupt request signal is input, clock oscillation starts, and stable clocks are supplied to the entire LSI after the time selected by the STS[4:0] bits in SBYCR has passed, software standby mode is canceled, and the interrupt exception handling is started.
Page 194: Example Of Software Standby Mode Application
RX610 Group 8. Low Power Consumption 8.5.3.3 Setting Oscillation Settling Time after Software Standby Mode is Canceled Set the STS[4:0] bits in SBYCR as follows: 1. When using a crystal resonator Set the STS[4:0] bits so that the waiting time is no less than the oscillation settling time. Table 8.4 shows operating frequencies and waiting time corresponding to each setting of the STS[4:0] bits.
Page 195: Deep Software Standby Mode
RX610 Group 8. Low Power Consumption 8.5.3.4 Example of Software Standby Mode Application Figure 8.2 shows an example where a transition to software standby mode is made at the falling edge on the IRQ pin, and software standby mode is canceled at the rising edge on the IRQ pin. In this example, an IRQ interrupt is accepted with the IRQMD[1:0] bits in IRQCRi of the ICU set to 01b (falling edge), and then the IRQMD[1:0] bits are set to 10b (rising edge).
Page 196: Canceling Deep Software Standby Mode
RX610 Group 8. Low Power Consumption 8.5.4 Deep Software Standby Mode 8.5.4.1 Transition to Deep Software Standby Mode When the WAIT instruction is executed with the SSBY bit in SBYCR set to 1, a transition to software standby mode* made. At this time, when the DPSBY bit in DPSBYCR is set to 1, a transition to deep software standby mode is made. However, if a software standby mode canceling source (NMI or IRQ0 to IRQ15) is generated concurrently when a transition to software standby mode is made, software standby mode is canceled regardless of the DPSBY setting, and the interrupt exception handling starts after the oscillation settling time for software standby mode specified by the...
Page 197: Setting Oscillation Settling Time After Deep Software Standby Mode Is Canceled
RX610 Group 8. Low Power Consumption 8.5.4.2 Canceling Deep Software Standby Mode Deep software standby mode is canceled by an external interrupt (NMI or IRQ0-A to IRQ3-A pins) or the reset signal from the RES# pin. 1. Canceling by an external interrupt The DPSIFR holds the cancelation cause of deep software standby mode and the bits in this register are set to 1 when the corresponding cancelation requests are generated.
Page 198: Example Of Deep Software Standby Mode Application
RX610 Group 8. Low Power Consumption 8.5.4.4 Setting Oscillation Settling Time after Deep Software Standby Mode is Canceled Set the WTSTS[5:0] bits in DPSWCR as follows: 1. When using a crystal resonator Set the WTSTS[5:0] bits so that the waiting time is no less than the oscillation settling time. Table 8.5 shows EXTAL input clock frequencies and waiting time corresponding to each setting of the WTSTS[5:0] bits.
Page 199: Flowchart To Use Deep Software Standby Mode
RX610 Group 8. Low Power Consumption 8.5.4.5 Example of Deep Software Standby Mode Application Figure 8.3 shows an example where a transition to deep software standby mode is made at the falling edge on the IRQ pin, and deep software standby mode is canceled at the rising edge on the IRQ pin. In this example, an IRQ interrupt is accepted with the IRQMD[1:0] bits in IRQCRi of the ICU set to 01 (falling edge), and then the DIRQnEG bit in DPSIEGR is set to 1 (rising edge).
Page 200 RX610 Group 8. Low Power Consumption 8.5.4.6 Flowchart to Use Deep Software Standby Mode Figure 8.4 shows an example of flowchart to use deep software standby mode. In this example, the DPSRSTF flag in RSTSR of the reset function is read after the reset exception handling to determine whether a reset was generated by the RES# pin or by the cancellation of deep software standby mode.
Page 201: Bclk Output Control
RX610 Group 8. Low Power Consumption BCLK Output Control The BCLK output can be controlled with the PSTOP1 bit in SCKCR and the B3 bit in P5.DDR of corresponding P53. When the PSTOP1 bit is cleared to 0, P53 functions as the BCLK output. When the PSTOP1 bit is set to 1, the BCLK output stops at the end of the bus cycle and goes high.
Page 202: Usage Notes
RX610 Group 8. Low Power Consumption Usage Notes 8.7.1 I/O Port States I/O port states are retained in software standby mode and deep software standby mode. Therefore, supply current is not reduced while output signals are held high. 8.7.2 Module Stop State of the DMAC and DTC Before setting the MSTPA28 or MSTPA27 bits in MSTPCRA to 1, clear the DMST bit in DMSCNT of the DMAC and the DTCST bit in DTCST of the DTC to 0 so that initiating transfer by the DTC or DMAC is not possible.
Page 203: Exceptions
RX610 Group 9. Exceptions Exceptions Types of Exceptions During the execution of a program by the CPU, the occurrence of certain events may necessitate suspending execution of the main flow of the program and starting the execution of another flow. Such events are called exceptions. The RX CPU supports the seven types of exceptions listed in figure 9.1.
Page 204: Undefined Instruction Exception
RX610 Group 9. Exceptions 9.1.1 Undefined Instruction Exception An undefined instruction exception occurs when execution of an undefined instruction (an instruction not implemented) is detected. 9.1.2 Privileged Instruction Exception A privileged instruction exception occurs when execution of a privileged instruction is detected while operation is in user mode.
Page 205: Exception Handling Procedure
RX610 Group 9. Exceptions Exception Handling Procedure For exception handling, part of the processing is handled automatically by hardware and part is handled by a program (the exception handling routine) that has been written by the user. Figure 9.2 shows the handling procedure when an exception other than a reset is accepted.
Page 206 RX610 Group 9. Exceptions When an exception is accepted, hardware processing by the RX CPU is followed by vector access to acquire the address of the branch destination. A vector address is allocated to each exception. The branch destination address of the handler for the given exception is written to each vector address.
Page 207: Acceptance Of Exceptions
RX610 Group 9. Exceptions Acceptance of Exceptions When an exception occurs, the CPU suspends the execution of the program and processing branches to the start of the exception handling routine. 9.3.1 Timing of Acceptance and Saved PC Values Table 9.1 lists the timing of acceptance and program counter (PC) value to be saved for each type of exception event. Table 9.1 Timing of Acceptance and Saved PC Value Timing of...
Page 208: Vector And Site For Saving The Values In The Pc And Psw
RX610 Group 9. Exceptions 9.3.2 Vector and Site for Saving the Values in the PC and PSW The vector for each type of exception and the site for saving the values of the program counter (PC) and processor status word (PSW) are listed in table 9.2. Table 9.2 Vector and Site for Saving the Values in the PC and PSW Site for Saving the Values in the...
Page 209: Hardware Processing For Accepting And Returning From Exceptions
RX610 Group 9. Exceptions Hardware Processing for Accepting and Returning from Exceptions This section describes the hardware processing for accepting and returning from exceptions other than a reset. Hardware pre-processing for accepting an exception Saving the values in the PSW •...
Page 210: Hardware Pre-Processing
RX610 Group 9. Exceptions Hardware Pre-Processing The sequences of hardware pre-processing from reception of each exception request to execution of the associated exception handling routine are explained below. 9.5.1 Undefined Instruction Exception 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2.
Page 211: Non-Maskable Interrupt
RX610 Group 9. Exceptions 9.5.5 Non-Maskable Interrupt 1. The value of the processor status word (PSW) is saved on the stack (ISP). 2. The processor mode select bit (PM), the stack pointer select bit (U), and the interrupt enable bit (I) in the PSW are cleared to 0.
Page 212: Return From Exception Handling Routines
RX610 Group 9. Exceptions Return from Exception Handling Routines Executing the instructions listed in table 9.3 at the end of the corresponding exception handling routines restores the values of the program counter (PC) and processor status word (PSW) that were saved on the stack or in the control registers (BPC and BPSW) immediately before the exception handling sequence.
Page 213: Interrupt Control Unit (Icu)
RX610 Group 10. ICU Interrupt Control Unit (ICU) 10.1 Overview The interrupt control unit (ICU) responds to interrupt signals from peripheral modules and external pins to convey interrupt requests to the CPU and activate the DTC and DMAC. Table 10.1 lists the specifications of the interrupt control unit, and figure 10.1 shows a block diagram of the interrupt control unit.
Page 214 RX610 Group 10. ICU Clock Interrupt control unit Clock restoration request generator Clock restoration judgment Clock restoration enable level Nonmaskable interrupt request NMI input block NMISR NMIER NMICR NMICLR Module data bus Interrupt request CPU priority level ISELR Interrupt reception judgment IRQER IRQCR...
Page 215: Register Descriptions
RX610 Group 10. ICU 10.2 Register Descriptions Table 10.3 lists the registers of the interrupt control unit. Table 10.3 Registers of the Interrupt Control Unit Register Name Symbol Value after Reset Address Access Size Interrupt request register 016 IR016 0008 7010h Interrupt request register 021 IR021 0008 7015h...
Page 216 RX610 Group 10. ICU Register Name Symbol Value after Reset Address Access Size Interrupt request register 122 IR122 0008 707Ah Interrupt request register 123 IR123 0008 707Bh Interrupt request register 124 IR124 0008 707Ch Interrupt request register 125 IR125 0008 707Dh Interrupt request register 126 IR126 0008 707Eh...
Page 217 RX610 Group 10. ICU Register Name Symbol Value after Reset Address Access Size Interrupt request register 182 IR182 0008 70B6h Interrupt request register 183 IR183 0008 70B7h Interrupt request register 184 IR184 0008 70B8h Interrupt request register 185 IR185 0008 70B9h Interrupt request register 198 IR198 0008 70C6h...
Page 218 RX610 Group 10. ICU Register Name Symbol Value after Reset Address Access Size Interrupt request destination setting register 031 ISELR031 0008 711Fh Interrupt request destination setting register 064 ISELR064 0008 7140h Interrupt request destination setting register 065 ISELR065 0008 7141h Interrupt request destination setting register 066 ISELR066 0008 7142h...
Page 219 RX610 Group 10. ICU Register Name Symbol Value after Reset Address Access Size Interrupt request destination setting register 158 ISELR158 0008 719Eh Interrupt request destination setting register 159 ISELR159 0008 719Fh Interrupt request destination setting register 161 ISELR161 0008 71A1h Interrupt request destination setting register 162 ISELR162 0008 71A2h...
Page 220 RX610 Group 10. ICU Register Name Symbol Value after Reset Address Access Size Interrupt request enable register 13 IER13 0008 7213h Interrupt request enable register 14 IER14 0008 7214h Interrupt request enable register 15 IER15 0008 7215h Interrupt request enable register 16 IER16 0008 7216h Interrupt request enable register 17...
Page 221 RX610 Group 10. ICU Register Name Symbol Value after Reset Address Access Size Interrupt priority register 52 IPR52 0008 7352h Interrupt priority register 53 IPR53 0008 7353h Interrupt priority register 54 IPR54 0008 7354h Interrupt priority register 55 IPR55 0008 7355h Interrupt priority register 56 IPR56 0008 7356h...
Page 222 RX610 Group 10. ICU Register Name Symbol Value after Reset Address Access Size IRQ detection enable register 5 IRQER5 0008 C305h IRQ detection enable register 6 IRQER6 0008 C306h IRQ detection enable register 7 IRQER7 0008 C307h IRQ detection enable register 8 IRQER8 0008 C308h IRQ detection enable register 9...
Page 223: Interrupt Request Register I (Iri) (I = Interrupt Vector Number)
RX610 Group 10. ICU 10.2.1 Interrupt Request Register i (IRi) (i = interrupt vector number) Addresses: 0008 7010h to 0008 70FDh — — — — — — — Value after reset: Symbol Bit Name Description Interrupt Status Flag 0: No interrupt request is generated R/(W)* 1: An interrupt request is generated ...
Page 224 RX610 Group 10. ICU • If the setting of the ISEL[1:0] bits in ISELRi is 10b, activation of the DMAC Level detection [Setting condition] • Generation of the interrupt signal from the source [Clearing conditions] • Clearing the status flag of the interrupt source •...
Page 225: Interrupt Request Destination Setting Register I (Iselri) (I = Interrupt Vector Number)
RX610 Group 10. ICU 10.2.2 Interrupt Request Destination Setting Register i (ISELRi) (i = interrupt vector number) Addresses: 0008 711Ch to 0008 71FDh — — — — — — ISEL[1:0] Value after reset: Symbol Bit Name Description b1, b0 ISEL[1:0] Interrupt R/W* b1 b0...
Page 226: Interrupt Request Enable Register M (Ieri) (I = 02H To 1Fh)
RX610 Group 10. ICU 10.2.3 Interrupt Request Enable Register m (IERi) (i = 02h to 1Fh) Addresses: 0008 7202h to 0008 721Fh IEN7 IEN6 IEN5 IEN4 IEN3 IEN2 IEN1 IEN0 Value after reset: Symbol Bit Name Description R/W* IEN0 Interrupt Request Enable 0 0: Interrupt request is disabled 1: Interrupt request is enabled IEN1...
Page 227: Interrupt Priority Register I (Ipri) (I = 00H To 8Fh)
RX610 Group 10. ICU 10.2.4 Interrupt Priority Register i (IPRi) (i = 00h to 8Fh) Addresses: 0008 7300h to 0008 738Fh — — — — — IPR[2:0] Value after reset: Symbol Bit Name Description b2 to b0 IPR[2:0] Interrupt Priority b2 b0 Level Select 0 0 0: Level 0 (interrupt prohibited)
Page 228: Fast Interrupt Register (Fir)
RX610 Group 10. ICU 10.2.5 Fast Interrupt Register (FIR) Address: 0008 73F0h — — — — — — — FIEN Value after reset: FVCT[7:0] Value after reset: Symbol Bit Name Description b7 to b0 FVCT[7:0] Fast Interrupt Specify the vector number of an interrupt source to be a fast Vector Number interrupt.
Page 229: Irq Detection Enable Register N (Irqern) (N = 0 To 15)
RX610 Group 10. ICU 10.2.6 IRQ Detection Enable Register n (IRQERn) (n = 0 to 15) Addresses: 0008 C300h to 0008 C30Fh — — — — — — — IRQEN Value after reset: Symbol Bit Name Description IRQEN IRQ Detection 0: Detection of the signal on the corresponding IRQn pin as an Enable external interrupt source is disabled...
Page 230: Irq Control Register N (Irqcrn) (N = 0 To 15)
RX610 Group 10. ICU 10.2.7 IRQ Control Register n (IRQCRn) (n = 0 to 15) Addresses: 0008 C320h to 0008 C32Fh — — — — IRQMD[1:0] — — Value after reset: Symbol Bit Name Description  b1, b0 Reserved These bits are read as 0. The write value should always be 0.
Page 231: Non-Maskable Interrupt Enable Register (Nmier)
RX610 Group 10. ICU 10.2.8 Non-maskable Interrupt Enable Register (NMIER) Address: 0008 C350h — — — — — — — NMIEN Value after reset: Symbol Bit Name Description NMIEN NMI Enable 0: NMI pin interrupt is disabled R/W* 1: NMI pin interrupt is enabled ...
Page 232: Nmi Pin Interrupt Control Register (Nmicr)
RX610 Group 10. ICU 10.2.9 NMI Pin Interrupt Control Register (NMICR) Address: 0008 C351h — — — — NMIMD — — — Value after reset: Symbol Bit Name Description  b2 to b0 Reserved These bits are read as 0. The write value should always be 0.
Page 233: Non-Maskable Interrupt Status Register (Nmisr)
RX610 Group 10. ICU 10.2.10 Non-maskable Interrupt Status Register (NMISR) Address: 0008 C352h — — — — — — — NMIST Value after reset: Symbol Bit Name Description NMIST NMI Status Flag 0: No NMI pin request is generated 1: An NMI pin request is generated ...
Page 234: Non-Maskable Interrupt Clear Register (Nmiclr)
RX610 Group 10. ICU 10.2.11 Non-maskable Interrupt Clear Register (NMICLR) Address: 0008 C353h — — — — — — — NMICLR Value after reset: Symbol Bit Name Description NMICLR NMI Clear This bit is always read as 0. R/W* Writing 1 to this bit clears the NMIST flag in NMISR. Writing 0 to this bit has no effect.
Page 235: Software Standby Release Irq Enable Register (Ssier)
RX610 Group 10. ICU 10.2.12 Software Standby Release IRQ Enable Register (SSIER) Address: 0008 C340h SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 Value after reset: SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 Value after reset: Symbol Bit Name Description SSI0 Software Standby Release...
Page 236: Vector Table
RX610 Group 10. ICU 10.3 Vector Table The interrupt control unit detects two types of interrupt exceptions: maskable interrupts and the non-maskable interrupt. When the CPU accepts an interrupt or non-maskable interrupt, it acquires a four-byte vector address from the vector table.
Page 237 RX610 Group 10. ICU Interrupt Selectable Interrupt Request Destination Request Vector Vector Address Form of Sstb Sacs DMAC Priority Source Name Number Offset Detection Recovery Recovery √ √ √ √ √ High External IRQ0 0100h Edge/Level ER08.IEN0 IPR20 ↑ √ √...
Page 238 RX610 Group 10. ICU Interrupt Selectable Interrupt Request Destination Request Vector Vector Address Form of Sstb Sacs DMAC Priority Source Name Number Offset Detection Recovery Recovery × × √ √ √ High TPU3 TGI3A 01E8h Edge ER0F.IEN2 IPR52 × × ×...
Page 239 RX610 Group 10. ICU Interrupt Selectable Interrupt Request Destination Request Vector Vector Address Form of Sstb Sacs DMAC Priority Source Name Number Offset Detection Recovery Recovery × × √ √ √ High TPU11 029Ch Edge TGI11A PR62 IER14. EN7 ↑ ×...
Page 240 RX610 Group 10. ICU Interrupt Selectable Interrupt Request Destination Request Vector Vector Address Form of Sstb Sacs DMAC Priority Source Name Number Offset Detection Recovery Recovery  × × × × ×   Reserved 033Ch IER19. EN7 High × ×...
Page 241: Fast Interrupt Vector Address
RX610 Group 10. ICU Interrupt Selectable Interrupt Request Destination Request Vector Vector Address Form of Sstb Sacs DMAC Priority Source Name Number Offset Detection Recovery Recovery × × × × √ High RIIC0 03D8h Level ICEEI0 IER1E.IEN6 PR88 ↑ × ×...
Page 242: Operation
RX610 Group 10. ICU 10.4 Operation The interrupt control unit determines priority levels of interrupts and non-maskable interrupts and outputs interrupt request signals to the CPU, DTC and/or DMAC. When the condition for the interrupt source is generated, the corresponding interrupt status flag (IR flag in IRi) is set and interrupt request signal is output to the request destination.
Page 243: Interrupt Status Flag
RX610 Group 10. ICU 10.4.2 Interrupt Status Flag The interrupt status flag (IR flag) in IRi detects the corresponding interrupt signal and retains an indication that the request was generated. There are two ways to detect interrupt sources: level detection and edge detection. For interrupts from peripheral modules, detection is by either edge or level according to the source.
Page 244: Interrupt Status Flag In Level Detection
RX610 Group 10. ICU Once the IR flag in IRi has been set to 1, even if the interrupt is disabled at its source, that is, if output of the interrupt is disabled by the interrupt enable bit of the corresponding peripheral module or detection of an external interrupt on pin IRQn is disabled by the IRQEN bit in IRQERn, the IR flag in IRi is not affected and retains its value.
Page 245 RX610 Group 10. ICU Figure 10.6 shows how the IR flag in IRi operates in the case of level detection of an external interrupt. If the setting of the IRQMD[1:0] bits in IRQCRn is for detection of the external interrupt as the low level of the signal, the interrupt source should maintain the low level on the IRQn pin until handling of the given interrupt.
Page 246: Selecting Interrupt Request Destinations
RX610 Group 10. ICU 10.4.3 Selecting Interrupt Request Destinations Sources that can act as interrupts or activate the DTC and DMAC have ISEL[1:0] bits in the corresponding ISELRi for setting the destination of interrupt requests. The selectable destinations for each of the interrupt sources are fixed and they are listed in table 10.4, Interrupt Vector Table.
Page 247 RX610 Group 10. ICU Notes: 1. Single-operand transfer is transfer for a single operand per activation request. The IR flag in IRi is cleared by activation of transfer for the single operand. In nonstop transfer, one round of DMA transfer proceeds per activation request.
Page 248: Determining Priority
RX610 Group 10. ICU 10.4.4 Determining Priority The interrupt control unit determines interrupt priority for each interrupt destination. If multiple interrupt requests are generated for the same destination, the interrupt from the highest priority source is accepted. The method used to determine the priority depends on the interrupt request destination. Determining Priority when Interrupt Request Destination is CPU For a group for which the ISEL[1:0] bits in ISELRi are set to 00b, the interrupt source with the larger value of the interrupt priority level select bits IPR[2:0] in IPRi takes precedence.
Page 249: External Interrupts
RX610 Group 10. ICU 10.4.6 External Interrupts External interrupts are interrupts that have the signals on the IRQn pins (n = 0 to 15) as sources. Figure 10.8 is a block diagram of the circuit for an external interrupt. Pm.ICR RQMD RQEN Low-level...
Page 250: Non-Maskable Interrupt Operation
RX610 Group 10. ICU 10.5 Non-maskable Interrupt Operation The interrupt on the non-maskable interrupt (NMI) pin serves as an NMI. Specifically, a rising or falling edge of the signal on the NMI pin issues an NMI request for the CPU. The DTC and DMAC are not selectable as destinations for the NMI.
Page 251: Returning From Low Power Consumption Modes
RX610 Group 10. ICU 10.6 Returning from Low Power Consumption Modes The interrupt control unit is capable of returning operation from low power consumption modes in response to interrupts. Table 10.5 shows the correspondence between low power consumption modes and the interrupt sources that are capable of initiating return from the individual modes.
Page 252: Returning From Software Standby Mode
RX610 Group 10. ICU 10.6.2 Returning from Software Standby Mode The interrupt control unit can return operation from software standby mode in response to the NMI or an external interrupt on the IRQn pins (n = 0 to 15). When the NMI or an IRQn (n = 0 to 15) external interrupt is generated, the clock starts oscillating and the clock signal is supplied throughout the LSI, and interrupt processing starts.
Page 253: Usage Notes
RX610 Group 10. ICU 10.7 Usage Notes 10.7.1 Notes when writing to the Register of the Interrupt Control Unit The CPU executes the following instruction without waiting for the completion of previous writing to the register of the interrupt control unit. Thus, the following instruction might be executed before the previously written value is stored in the register.
Page 254 RX610 Group 10. ICU Table 10.6 Setting Conditions of the DMAC/DTC and Occurrence of the Phenomenon Destination of Interrupt Request Chain Transfer Used or Not Communication Interrupts to Possibility of Problem from Communication Function Used CPU Issued or Not Issued Occurrence DMAC —...
Page 255 RX610 Group 10. ICU Transmit/receive interrupt Determine internal source in Multiple-interrupt communication*1 disabled Software preventive measures Set IRi.IR to 1 Set PSW.I to 1*2 Note 1. Determination of internal source in communication Communication Receive Buffer Full Flag Transmit Buffer Empty Flag Function SSR.RDRF=1 SSR.TDRE=1...
Page 256: Buses
RX610 Group 11. Buses Buses 11.1 Overview Table 11.1 lists the bus specifications and figure 11.1 shows the bus configuration. Table 11.1 Bus Specifications Bus Type Description • CPU bus Instruction bus Connected to the CPU (for instructions) • Connected to on-chip memory (on-chip RAM, on-chip ROM) •...
Page 257: Description Of Buses
RX610 Group 11. Buses 11.2 Description of Buses 11.2.1 CPU Buses The CPU buses consist of the instruction and operand buses, which are connected to internal main bus 1. As the names suggest, the instruction bus is used to fetch instructions for the CPU, while the operand bus is used for operand access. Connection of the instruction and operand buses to on-chip RAM and on-chip ROM provides the CPU with direct access to these areas, i.e.
Page 258: Internal Peripheral Buses
RX610 Group 11. Buses 11.2.3 Internal Peripheral Buses Connection of peripheral modules to the internal peripheral buses is as described in table 11.3. Table 11.3 Connection of Peripheral Modules to the Internal Peripheral Buses Type of Bus Peripheral Modules • Internal peripheral bus 1 DMAC •...
Page 259 RX610 Group 11. Buses Table 11.5 shows the input/output pins of the external bus. Table 11.5 Pin Configuration of the External Bus Pin Name Description A23 to A0 Output Address output pins *1 *2 BC0# Output A strobe signal; (the BC0# signal being at the low level) during access to an external address space in single write strobe mode indicates that the lower-order byte (D7 to D0) is valid.
Page 260: Parallel Operation
RX610 Group 11. Buses 11.2.5 Parallel Operation Parallel operation is possible when different bus-master modules are requesting access to different slave modules. For example, if the CPU is fetching an instruction from on-chip ROM and an operand from on-chip RAM, the DMAC is able to handle transfer between a peripheral bus and the external bus at the same time.
Page 261: Register Descriptions
RX610 Group 11. Buses 11.3 Register Descriptions Table 11.6 lists the registers of the external bus controller. Table 11.6 Registers of the External Bus Controller Register Name Symbol Value after Reset Address Access Size CS0 control register CS0CNT 0021h 0008 3802h CS0 recovery cycle register CS0REC 0000h...
Page 262 RX610 Group 11. Buses Register Name Symbol Value after Reset Address Access Size CS6 mode register CS6MOD 0000h 0008 3062h CS6 wait control register 1 CS6WCNT1 0707 0707h 0008 3064h CS6 wait control register 2 CS6WCNT2 0000 0007h 0008 3068h CS7 mode register CS7MOD 0000h...
Page 263: Csi Control Register (Csicnt) (I = 0 To 7)
RX610 Group 11. Buses 11.3.1 CSi Control Register (CSiCNT) (i = 0 to 7) Address: 0008 3802h (CS0CNT) — — — — — — — — — — — — EMODE EXENB BSIZE[1:0] Value after reset: Addresses: 0008 3812h to 0008 3872h (CS1CNT to CS7CNT) —...
Page 264 RX610 Group 11. Buses EMODE Bit (Endian Mode) This bit specifies the endian of each area. When the endian setting for each area is different from that for the chip, no instruction code can be allocated in the area. If the instruction code is allocated to the external address space, it must be allocated to areas where the endian setting is the same as that for the chip.
Page 265: Csi Recovery Cycle Register (Csirec) (I = 0 To 7)
RX610 Group 11. Buses 11.3.2 CSi Recovery Cycle Register (CSiREC) (i = 0 to 7) Addresses: 0008 380Ah to 0008 387Ah — — — — — — — — WRCV[3:0] RRCV[3:0] Value after reset: Symbol Bit Name Description b3 to b0 RRCV[3:0] Read Recovery 0: No recovery cycle is inserted.
Page 266 RX610 Group 11. Buses RRCV[3:0] Bits (Read Recovery) These bits specify the number of recovery cycles to be inserted after a read access to the external bus. When a value except 0000b is written to these bits, one to 15 recovery cycles are inserted in the following cases. •...
Page 267: Csi Mode Register (Csimod) (I = 0 To 7)
RX610 Group 11. Buses 11.3.3 CSi Mode Register (CSiMOD) (i = 0 to 7) Addresses: 0008 3002h to 0008 3072h — — — — — — — — — — — PRMOD PWENB PRENB EWENB WRMOD Value after reset: Symbol Bit Name Description WRMOD...
Page 268 RX610 Group 11. Buses EWENB Bit (External Wait Enable) This bit enables or disables external wait. Writing 1 to this bit selects external wait and allows control of the number of waits in each cycle with the WAIT# signal. In this state, wait cycles are inserted while the WAIT# signal is at the low level. Writing 0 to this bit disables the WAIT# signal.
Page 269: Csi Wait Control Register 1 (Csiwcnt1) (I = 0 To 7)
RX610 Group 11. Buses 11.3.4 CSi Wait Control Register 1 (CSiWCNT1) (i = 0 to 7) Addresses: 0008 3004h to 0008 3074h — — — — — — CSRWAIT[4:0] CSWWAIT[4:0] Value after reset: — — — — — — — —...
Page 270 RX610 Group 11. Buses Symbol Bit Name Description b20 to b16 Normal Write CSWWAIT[4:0] 0: No wait is inserted. Cycle Wait 1: Wait with a length of 1 clock cycle is inserted. Select 0: Wait with a length of 2 clock cycles is inserted. 1: Wait with a length of 3 clock cycles is inserted.
Page 271 RX610 Group 11. Buses Symbol Bit Name Description b28 to b24 CSRWAIT[4:0] Normal 0: No wait is inserted. Read 1: Wait with a length of 1 clock cycle is inserted. Cycle Wait 0: Wait with a length of 2 clock cycles is inserted. Select 1: Wait with a length of 3 clock cycles is inserted.
Page 272 RX610 Group 11. Buses CSPRWAIT[2:0] Bits (Page Read Cycle Wait Select) These bits specify the number of wait cycles to be inserted into the second and subsequent accesses during a page read cycle. This setting is enabled when the PRENB bit in CSiMOD is set to 1. Note: Set these bits so that CSON[2:0] ≤...
Page 273: Csi Wait Control Register 2 (Csiwcnt2) (I = 0 To 7)
RX610 Group 11. Buses 11.3.5 CSi Wait Control Register 2 (CSiWCNT2) (i = 0 to 7) Addresses: 0008 3008h to 0008 3078h — — — — CSON[2:0] WDON[2:0] WRON[2:0] RDON[2:0] Value after reset: — — — — — — — WDOFF[2:0] CSWOFF[2:0] CSROFF[2:0]...
Page 274 RX610 Group 11. Buses Symbol Bit Name Description b18 to b16 RDON[2:0] RD Assert Wait Select 0: No wait is inserted. 1: Wait with a length of 1 clock cycle is inserted. 0: Wait with a length of 2 clock cycles is inserted. 1: Wait with a length of 3 clock cycles is inserted.
Page 275 RX610 Group 11. Buses CSROFF[2:0] Bits (Read-Access CS Extension Cycle Select) These bits specify the number of wait cycles to be inserted in a time period from the end of a wait cycle (RD# signal negated) until the CSi# signal (i = 0 to 7) is negated in read access mode. CSWOFF[2:0] Bits (Write-Access CS Extension Cycle Select) These bits specify the number of wait cycles to be inserted in a time period from the end of a wait cycle (WR0#, WR1#, or WR# signal negated) until the CSi# signal (i = 0 to 7) is negated in write access mode.
Page 276 RX610 Group 11. Buses CSON[2:0] Bits (CS Assert Wait Select) These bits specify the number of wait cycles to be inserted before the CSi# signal (i = 0 to 7) is asserted. Note: Set these bits so that the following conditions are satisfied: CSON[2:0] ≤...
Page 277: Bus Error Source Clear Register (Berclr)
RX610 Group 11. Buses 11.3.6 Bus Error Source Clear Register (BERCLR) Address: 0008 1300h — — — — — — — STSCLR Value after reset: Symbol Bit Name Description STSCLR Bus Error Source Clear 0: No effect R/(W)* 1: Clears the bus-error source signals ...
Page 278: Bus Error Interrupt Enable Register (Berie)
RX610 Group 11. Buses 11.3.8 Bus Error Interrupt Enable Register (BERIE) Address: 0008 1306h — — — — — — — CPEN Value after reset: Symbol Bit Name Description CPEN CPU Bus Error 0: Bus-error interrupts are not conveyed to the CPU. Notification Control 1: Bus-error interrupts are conveyed to the CPU.
Page 279: Endian And Data Alignment
RX610 Group 11. Buses 11.4 Endian and Data Alignment Eight, 16, and 32 bits are the units of access by the CPU and other internal bus-master modules. The external bus controller has a data-alignment facility, and this can control whether access is to bits D15 to D8 or to bits D7 to D0, the bus specification (8-bit or 16-bit bus space), the unit of access, and the endian for areas of the external address space.
Page 280: 8-Bit Bus Space
RX610 Group 11. Buses WR1#/BC1# WR0#/BC0# Number of Data Bus Bus Cycle Unit of Data Address Data Size Access Address Access First 8 bits 4n+1 First 8 bits 8 bits 4n+2 First 8 bits 4n+2 4n+3 First 8 bits 4n+2 First 16 bits First...
Page 281 RX610 Group 11. Buses WR1#/BC1# WR0#/BC0# Data Bus Access Number of Bus Cycle Unit of Data Address Data Size Address Access First 8 bits 4n+1 First 8 bits 4n+1 8 bits 4n+2 First 8 bits 4n+2 4n+3 First 8 bits 4n+3 First 8 bits...
Page 282 RX610 Group 11. Buses WR1#/BC1# WR0#/BC0# Data Bus Access Number of Bus Cycle Unit of Data Address Data Size Address Access First 8 bits 4n+1 First 8 bits 4n+1 8 bits 4n+2 First 8 bits 4n+2 4n+3 First 8 bits 4n+3 First 8 bits...
Page 283: Operation
RX610 Group 11. Buses 11.5 Operation 11.5.1 Timing of External Bus Access The various periods in the timing charts are described below. (1) Tw1 to Twn (clock cycles of waiting for a normal read cycle or normal write cycle) The period Tw1 to Twn is made up of the number of clock cycles between the start of access via the external bus and the cycle where waiting is completed (described below).
Page 284 RX610 Group 11. Buses (3) Tn1 to Tnm (clock cycles of CS extension) In the case of normal access, Tn1 to Tnm represent the clock cycles of the period following the cycle where the strobe signal is valid (Tend) up to negation of the CSi# signal. For read or write access, the timing of negation is controlled by the CS extension cycles setting for reading (CSROFF) or the CS extension cycles setting for writing (CSROFF) in CSi wait control register 2 (CSiWCNT2).
Page 285: Normal Access
RX610 Group 11. Buses (7) Tr1 to Trn (clock cycles of recovery) Clock cycles of recovery can be inserted from the point where a bus cycle is completed. The number of clock cycles is controlled by the setting of the read recovery (RRCV) or write recovery (WRCV) bits in the CSi recovery cycle setting register (CSiREC).
Page 286 RX610 Group 11. Buses Next bus access can be started Tend External bus clock (BCLK) Write-access CS extension cycle (CSWOFF) Normal read cycle wait (CSWWAIT) Address (A23 to A0) CS assert wait (CSON) Chip select/byte control (CSn#/BC0#, BC1#) WR assert wait (WRON) Data read (WR0#, WR1#, WR#) Write data output wait (WDON)
Page 287 RX610 Group 11. Buses When two or more rounds of external bus access are required in response to a single request for transfer from a bus master, normal access operations (points 1. to 4. above) are repeated. Figures 11.10 and 11.11 show examples of operations when two rounds of bus access are generated in response to a single request for transfer.
Page 288 RX610 Group 11. Buses Tend Tend External bus clock (BCLK) Normal read cycle wait (CSRWAIT): 2 CSRWAIT: 2 Address (A23 to A0) CSROFF: 1 Read-access CS extension cycle (CSROFF): 1 Chip select (CSn#) Byte control 1 (BC1#) Byte control 0 (BC0#) RD assert wait (RDON): 1 RDON: 1...
Page 289 RX610 Group 11. Buses Tend Tend External bus clock (BCLK) Normal write cycle wait (CSWWAIT): 2 CS assert wait CSWWAIT: 2 (CSON): 0 Address (A23 to A0) Write-access CS extension cycle (CSWOFF): 1 CSWOFF: 1 Chip select (CSn#) Byte control 1 (BC1#) Byte control 0 (BC0#)
Page 290: Page Access
RX610 Group 11. Buses 11.5.1.2 Page Access When the PRENB and PWENB bits in CSiMOD are set to 1 to enable page-reading and page-writing access, respectively, the bus access for page access operations becomes page reading and writing. Page access is made when two or more rounds of external bus access are required for a single transfer request from the bus master.
Page 291 RX610 Group 11. Buses Next bus access can be started Tend Tdw1 Tdwn Tpw1 Tpwn Tend External bus clock (BCLK) Write-access CS extension Write cycle wait Page write cycle wait (CSWWAIT) (CSPWWAIT) cycle(CSWOFF) Address (A23 to A0) CS assert wait (CSON) Chip select/byte control (CSn#/BC0#, BC1#) WR assert wait (WRON)
Page 292 RX610 Group 11. Buses Accessed in 32 bits Accessed in 32 bits Tend Tpw1 Tend Tend Tend Tpw1 External bus clock (BCLK) Address (A23 to A0) CSWOFF: 1 Chip select/byte control CSWWAIT: 1 CSPWWAIT: 1 CSWWAIT: 1 CSPWWAIT: 1 CSWOFF: 1 (CSn#/BC0#, BC1#) Data write WRON: 1...
Page 293: External Wait Function
RX610 Group 11. Buses 11.5.2 External Wait Function Wait cycles can be extended by the WAIT# signal over the length of normal access cycle wait (specified by the CSRWAIT[4:0] and CSWWAIT[4:0] bits in CSiWCNT1) and page access cycle wait (specified by the CSPRWAIT[2:0] and CSPWWAIT[2:0] bits in CSiWCNT1).
Page 294 RX610 Group 11. Buses (Tend) Tend Tdw1 Tpw1 Tpwn (Tend) Tend Tdw1 External bus clock (BCLK) Address (A23 to A0) Chip select/byte control (CSn#/BC0#, BC1#) Data read (RD#) WR assert wait (WRON) WR assert wait (WRON) Data write (WR0#, WR1#, WR#) Page write cycle wait (CSPWWAIT) Normal Write cycle wait (CSWWAIT) Data bus...
Page 295: Insertion Of Recovery Cycles
RX610 Group 11. Buses 11.5.3 Insertion of Recovery Cycles Clock cycles of recovery can be inserted between consecutive rounds of external bus access. Conditions where cycles of recovery can be inserted are described below. • Write access via the external bus follows read access via the external bus. •...
Page 296: Write Buffer Function
RX610 Group 11. Buses 11.5.4 Write Buffer Function The internal main bus is released by writing data to the write buffer before the write access is completed, which allows the next round of bus access to start. However, if the following round of bus access is to an external address space or to a control register for the external bus, it is suspended until the external bus operations already in progress are completed.
Page 297: Notes On Usage
RX610 Group 11. Buses 11.5.5 Notes on Usage 11.5.5.1 Limitations at the Time of Normal and Page Access Limitations that apply to various bits of CSi wait control register 1 (CSiWCNT1) and CSi wait control register 2 (CSiWCNT2) at the times of normal and page access are listed in table 11.9. If the setting of the page-read access enable bit in the CSi mode register or the page-write access enable bit in the CSi mode register selects permission (CSiMOD.PRENB = 1 or CSiMOD.PWENB = 1), the limitations on normal access must be satisfied in the first round of access for page access or in access that does not fall within the scope of page access...
Page 298: Restriction On Instruction Code
RX610 Group 11. Buses 11.5.5.5 Restriction on Instruction Code When the endian setting for an area is different from that for the chip, no instruction code can be arranged in the area. The instruction code should be arranged in the external address space whose endian setting is the same as that for the chip.
Page 299: Bus Error Monitoring Section
RX610 Group 11. Buses 11.6 Bus Error Monitoring Section The bus-error monitoring section monitors the individual areas for bus errors, and generates an interrupt when it detects a bus error. 11.6.1 Types of Bus Error There are two types of bus error: illegal address access and time-out. Illegal address access is the detection of illegal access to an area, and time-out is the detection of a bus-access operation not being completed within 768 cycles.
Page 300: Conditions Leading To Bus Errors
RX610 Group 11. Buses 11.6.3 Conditions Leading to Bus Errors Table 11.10 lists the types of bus errors for each area in the respective address space. Table 11.10 Types of Bus Errors Type of Error Type of Area Illegal Address Access Time-out On-chip ROM Mode On-chip ROM mode...
Page 301: Dma Controller (Dmac)
RX610 Group 12. DMA Controller (DMAC) DMA Controller (DMAC) The RX610 Group incorporates a 4-channel direct memory access controller (DMAC). The DMAC is a module to transfer data without the CPU. When a DMA transfer request is generated, the DMAC transfers data stored at the transfer source address to the transfer destination address.
Page 302 RX610 Group 12. DMA Controller (DMAC) Item Description Selective function Reload function Reloads the values in reload registers (transfer source address, transfer destination address, transfer byte count) to current registers (transfer source address, transfer destination address, transfer byte count) at the end of DMA transfer.
Page 303: Register Descriptions
RX610 Group 12. DMA Controller (DMAC) 12.2 Register Descriptions Table 12.2 lists the registers of the DMAC. Registers of DMAC0 to DMAC3 have same functions. Table 12.2 Registers of DMAC Value after Access Channel Register Name Symbol Reset Address Size DMAC0 DMA mode register DMMOD...
Page 304 RX610 Group 12. DMA Controller (DMAC) Value after Access Channel Register Name Symbol Reset Address Size DMAC3 DMA mode register DMMOD 0x0x xx00h 0008 203Ch DMA control register A DMCRA 0000 0000h 0008 2418h DMA control register B DMCRB 0008 241Ch DMA control register C DMCRC 0008 241Dh...
Page 305: Dma Mode Register (Dmmod)
RX610 Group 12. DMA Controller (DMAC) 12.2.1 DMA Mode Register (DMMOD) Addresses: DMAC0.DMMOD 0008 200Ch, DMAC1.DMMOD 0008 201Ch DMAC2.DMMOD 0008 202Ch, DMAC3.DMMOD 0008 203Ch — — — — OPSEL[3:0] — — — — — SZSEL[2:0] Value after reset: — SMOD[2 0] —...
Page 306 RX610 Group 12. DMA Controller (DMAC) Symbol Bit Name Description b27 to b24 OPSEL[3:0] Operand Transfer Data Count Select b27 b26 b25 b24 0: Single data 1: 2 data 0: 4 data 1: 8 data 0: 16 data 1: 32 data 0: 64 data 1: 128 data Do not write other values.
Page 307: Dma Control Register A (Dmcra)
RX610 Group 12. DMA Controller (DMAC) 12.2.2 DMA Control Register A (DMCRA) Addresses: DMAC0.DMCRA 0008 2400h, DMAC1.DMCRA 0008 2408h DMAC2.DMCRA 0008 2410h, DMAC3.DMCRA 0008 2418h DSEL[1:0] — — — — — — — — — — — — — — Value after reset: BRLOD SRLOD DRLOD DCTG[5:0]...
Page 308 RX610 Group 12. DMA Controller (DMAC) Table 12.4 Setting of DCTG[5:0] Bits DMA Activation Source DCTG[5:0] Bits DMA0 DMA1 DMA2 DMA3 000000 Software trigger 000001 CMI0 (CMT0 compare match interrupt of compare match timer unit 0) 000010 CMI1 (CMT1 compare match interrupt of compare match timer unit 0) 000011 CMI2 (CMT2 compare match interrupt of compare match timer unit 1) 000100...
Page 309 RX610 Group 12. DMA Controller (DMAC) enabling register in the ICU (IERi; i = 02h to 1Fh) must be set to 1, and the relevant interrupt destination setting register of the ICU (ISELRi, where n is the interrupt vector number) must be set to select the DMAC as the destination of the interrupt signal.
Page 310: Dma Control Register B (Dmcrb)
RX610 Group 12. DMA Controller (DMAC) 12.2.3 DMA Control Register B (DMCRB) Addresses: DMAC0.DMCRB 0008 2404h, DMAC1.DMCRB 0008 240Ch DMAC2.DMCRB 0008 2414h, DMAC3.DMCRB 0008 241Ch — — — — — — — DSCLR Value after reset: Symbol Bit Name Description DSCLR DMAC Internal Status Clear Writing 1 to this bit initializes the DMAC internal status.
Page 311: Dma Control Register C (Dmcrc)
RX610 Group 12. DMA Controller (DMAC) 12.2.4 DMA Control Register C (DMCRC) Addresses: DMAC0.DMCRE 0008 2407h, DMAC1.DMCRE 0008 240Fh DMAC2.DMCRE 0008 2417h, DMAC3.DMCRE 0008 241Fh — — — — — — — Value after reset: Symbol Bit Name Description ECLR DMA Transfer Enable Clear 0: The DEN bit is not cleared to 0 at the end of DMA transfer.
Page 312: Dma Control Register D (Dmcrd)
RX610 Group 12. DMA Controller (DMAC) 12.2.5 DMA Control Register D (DMCRD) Addresses: DMAC0.DMCRD 0008 2406h, DMAC1.DMCRD 0008 240Eh DMAC2.DMCRD 0008 2416h, DMAC3.DMCRD 0008 241Eh — — — — — — — DREQ Value after reset: Symbol Bit Name Description DREQ DMA Transfer Request 0: No DMA transfer request is generated...
Page 313: Dma Control Register E (Dmcre)
RX610 Group 12. DMA Controller (DMAC) 12.2.6 DMA Control Register E (DMCRE) Addresses: DMAC0.DMCRE 0008 2407h, DMAC1.DMCRE 0008 240Fh DMAC2.DMCRE 0008 2417h, DMAC3.DMCRE 0008 241Fh — — — — — — — Value after reset: Symbol Bit Name Description DMA Transfer Enable 0: DMA transfer is disabled 1: DMA transfer is enabled ...
Page 314: Dma Current Transfer Source Address Register (Dmcsa)
RX610 Group 12. DMA Controller (DMAC) 12.2.7 DMA Current Transfer Source Address Register (DMCSA) Addresses: DMAC0.DMCSA 0008 2000h, DMAC1.DMCSA 0008 2010h DMAC2.DMCSA 0008 2020h, DMAC3.DMCSA 0008 2030h Value after reset: Value after reset: Note: x: Undefined Description Setting Range b31 to b0 Transfer source start address 00000000h to FFFFFFFFh (4 Gbytes) DMCSA is used to set the start address of the transfer source.
Page 315: Dma Current Transfer Destination Address Register (Dmcda)
RX610 Group 12. DMA Controller (DMAC) 12.2.8 DMA Current Transfer Destination Address Register (DMCDA) Addresses: DMAC0.DMCDA 0008 2004h, DMAC1.DMCDA 0008 2014h DMAC2.DMCDA 0008 2024h, DMAC3.DMCDA 0008 2034h Value after reset: Value after reset: Note: x: Undefined Description Setting Range b31 to b0 Transfer destination start address 00000000h to FFFFFFFFh (4 Gbytes) DMCDA is used to set the start address of the transfer destination.
Page 316: Dma Current Transfer Byte Count Register (Dmcbc)
RX610 Group 12. DMA Controller (DMAC) 12.2.9 DMA Current Transfer Byte Count Register (DMCBC) Addresses: DMAC0.DMCBC 0008 2008h, DMAC1.DMCBC 0008 2018h DMAC2.DMCBC 0008 2028h, DMAC3.DMCBC 0008 2038h — — — — — — Value after reset: Value after reset: Note: x: Undefined Description Setting Range b25 to b0...
Page 317: Dma Reload Transfer Source Address Register (Dmrsa)
RX610 Group 12. DMA Controller (DMAC) 12.2.10 DMA Reload Transfer Source Address Register (DMRSA) Addresses: DMAC0.DMRSA 0008 2200h, DMAC1.DMRSA 0008 2210h DMAC2.DMRSA 0008 2220h, DMAC3.DMRSA 0008 2230h Value after reset: Value after reset: Note: x: Undefined Description Setting Range b31 to b0 Set an address value to be reloaded to the DMCSA register of 00000000h to FFFFFFFFh (4 Gbytes) DMACm...
Page 318: Dma Reload Transfer Byte Count Register (Dmrbc)
RX610 Group 12. DMA Controller (DMAC) 12.2.12 DMA Reload Transfer Byte Count Register (DMRBC) Addresses: DMAC0.DMRBC 0008 2208h, DMAC1.DMRBC 0008 2218h DMAC2.DMRBC 0008 2228h, DMAC3.DMRBC 0008 2238h — — — — — — Value after reset: Value after reset: Note: x: Undefined Description Setting Range b25 to b0...
Page 319: Dma Interrupt Control Register (Dmicnt)
RX610 Group 12. DMA Controller (DMAC) 12.2.13 DMA Interrupt Control Register (DMICNT) Address: 0008 250Bh DINTM0 DINTM1 DINTM2 DINTM3 — — — — Value after reset: Symbol Bit Name Description  b3 to b0 Reserved These bits are always read as 0. The write value should always be DINTM3 DMA3 Interrupt Enable 0: DMAm interrupts are disabled...
Page 320: Dma Start Register (Dmscnt)
RX610 Group 12. DMA Controller (DMAC) 12.2.14 DMA Start Register (DMSCNT) Address: 0008 2502h — — — — — — — DMST Value after reset: Symbol Bit Name Description DMST DMAC Start 0: DMAC stop 1: DMAC start  b7 to b1 Reserved These bits are always read as 0.
Page 321: Dma Arbitration Status Register (Dmasts)
RX610 Group 12. DMA Controller (DMAC) 12.2.15 DMA Arbitration Status Register (DMASTS) Address: 0008 251Bh DASTS0 DASTS1 DASTS2 DASTS3 — — — — Value after reset: Symbol Bit Name Description  b3 to b0 Reserved These bits are always read as 0. Do not write to this bit. DASTS3 Channel 3 Arbitration Status Flag 0: Data transfer is not in progress...
Page 322: Dma Transfer End Detect Register (Dmedet)
RX610 Group 12. DMA Controller (DMAC) 12.2.16 DMA Transfer End Detect Register (DMEDET) Address: 0008 2517h DEDET0 DEDET1 DEDET2 DEDET3 — — — — Value after reset: Symbol Bit Name Description  b3 to b0 Reserved These bits are always read as 0. The write value should always be 0.
Page 323: Operation
RX610 Group 12. DMA Controller (DMAC) 12.3 Operation 12.3.1 Bus Mastership Release Timing The DMAC must release bus mastership for an interval of at least one cycle per single operation of data reading and writing. The bus is thus accessible by another master (CPU or DTC) during this interval. Furthermore, access by the CPU (except with the DMAC as the target) is possible during access by the DMAC.
Page 324: Transfer System
RX610 Group 12. DMA Controller (DMAC) 12.3.2 Transfer System The DMA transfer system includes operand transfer and nonstop transfer. The operand transfer system includes single-operand transfer and consecutive-operand transfer. The single-operand transfer allows transfer of a single operand per DMA transfer request, and the consecutive-operand transfer allows transfer in operand units upon a DMA transfer request until the DMA transfer ends.
Page 325 RX610 Group 12. DMA Controller (DMAC) Single-operand transfer Channel arbitration Channel arbitration Channel arbitration Channel arbitration Channel arbitration "1" DMACm.DMCRD.DREQ bit "0" Single DMA transfer Single-operand transfer Single-operand transfer Single-operand transfer Single-operand transfer Channel m Single data 0000008h 0000006h 0000004h 0000002h 0000000h DMACm.DMCBC register...
Page 326: Activating The Dmac
RX610 Group 12. DMA Controller (DMAC) 12.3.3 Activating the DMAC Figure 12.4 shows the register setting procedure. Start initial settings <When peripheral function interrupt is used as a DMA activation source> Set the peripheral function to be a DMAm request source Set the peripheral function control register, but do not start the DMAC.
Page 327: Starting Dma Transfer
RX610 Group 12. DMA Controller (DMAC) 12.3.4 Starting DMA Transfer Setting the DEN bit in DMCRE of DMACm to 1 (DMA transfer enabled) and setting the DMST bit in DMSCNT to 1 (DMAC start) enable DMA transfer of channel m (m = 0 to 3). When DMA transfer requests are generated, channel arbitration is made where a DMA transfer request of higher-priority channel is accepted and DMA transfer of the channel starts.
Page 328: Suspending, Restarting, And Canceling Dma Transfer
RX610 Group 12. DMA Controller (DMAC) 12.3.6 Suspending, Restarting, and Canceling DMA Transfer (1) Suspending DMA transfer DMA transfer by operand transfer can be suspended by clearing the DMST (DMAC stop) bit in DMSCNT or the DEN bit in DMCRE for DMACm to 0 (disabling DMA transfer on that channel). Suspension applies to all channels when the DMST bit is 0 or the corresponding channel n when DEN bit is 0, and becomes effective on completion of the transfer for the operand for which transfer was in progress.
Page 329: Dma Activation Source
RX610 Group 12. DMA Controller (DMAC) 12.3.7 DMA Activation Source Interrupt signals from peripheral functions and interrupt signals on external pins for which the appropriate software-trigger and interrupt control unit (ICU) settings have been made are selectable as DMA activation sources. 12.3.7.1 Software Trigger When software trigger is selected as a DMA activation source and the DREQ bit in DMCRD of DMACm is set to 1 (a...
Page 330: Channel Arbitration
RX610 Group 12. DMA Controller (DMAC) 12.3.8 Channel Arbitration When multiple DMA transfer requests are present, the DMAC determines the priority of channels that have DMA transfer requests. The channel priority is fixed as channel 0 > channel 1 > channel 2 > channel 3 (channel 0: highest). When a DMA transfer request is generated during data transfer, channel arbitration is started at the beginning of final data write access.
Page 331: Rotate
RX610 Group 12. DMA Controller (DMAC) 12.3.10 Rotate When "rotate" is selected with the DMOD[2:0] and SMOD[2:0] bits in DMMOD of DMACm, transfer destination and source addresses are automatically increased during data transfer. The values written at the beginning of DMA transfer are reloaded to the address registers when single-operand transfer is completed.
Page 332: Low-Power Consumption
RX610 Group 12. DMA Controller (DMAC) 12.5 Low-Power Consumption If the DMAC is to be placed in any low power-consumption state (module-stop state, all-module clock-stop mode, software-standby mode, or deep software-standby mode), DMAC transfer in progress when the request for transition to the low-power state was accepted must be suspended.
Page 333: Usage Notes
RX610 Group 12. DMA Controller (DMAC) 12.6 Usage Notes 12.6.1 Register Settings (1) When setting the bits or registers below, set them when the DASTSm flag (m = 0 to 3) in DMASTS is 0 (data transfer is not in progress) and the DEN bit in DMCRE of DMACm is 0 (DMA transfer disabled) or when the DMST bit in DMSCNT is 0 (DMAC stop) for the target channel.
Page 334: Data Transfer Controller (Dtc)
RX610 Group 13. Data Transfer Controller (DTC) Data Transfer Controller (DTC) The RX610 Group incorporates a data transfer controller (DTC). The DTC is activated by an interrupt request and controls data transfer. 13.1 Overview Table 13.1 lists the specifications of the DTC, and figure 13.1 shows a block diagram of the DTC. Table 13.1 DTC Specifications Item...
Page 335 RX610 Group 13. Data Transfer Controller (DTC) Register Interrupt control unit Transfer data mode control Vector number DTCCR Vector base address DTCVBR Start request Startup DTCADMOD control Stop request DTCST Bus interface DTC response response control External bus On-chip RAM Peripheral bus External bus Bus master...
Page 336: Register Descriptions
RX610 Group 13. Data Transfer Controller (DTC) 13.2 Register Descriptions Table 13.2 lists the registers of the DTC. Registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be accessed directly from the CPU. They are located in the data area as transfer data. When a DTC activation request is generated, the transfer data start address is read according to the vector address determined for each startup source, and arbitrary transfer data is transferred in the DTC.
Page 337: Dtc Mode Register A (Mra)
RX610 Group 13. Data Transfer Controller (DTC) 13.2.1 DTC Mode Register A (MRA) Address (inaccessible directly from the CPU) — — MD[1:0] SZ[1:0] SM[1:0] Value after reset: [Legend] x: Undefined Symbol Symbol   b1, b0 Reserved The read data is undefined. The write value should be 0. ...
Page 338: Dtc Mode Register B (Mrb)
RX610 Group 13. Data Transfer Controller (DTC) 13.2.2 DTC Mode Register B (MRB) Address (inaccessible directly from the CPU) — — CHNE CHNS DISEL DM[1:0] Value after reset: [Legend] x: Undefined Symbol Bit Name Description   b1, b0 Reserved The read data is undefined.
Page 339: Dtc Source Address Register (Sar)
RX610 Group 13. Data Transfer Controller (DTC) CHNS Bit (DTC Chain Transfer Select) The CHNS bit selects the chain transfer condition. When the next transfer is chain transfer, completion of specified transfer count is not checked and the startup source flag is not cleared.
Page 340: Dtc Transfer Count Register A (Cra)
RX610 Group 13. Data Transfer Controller (DTC) 13.2.5 DTC Transfer Count Register A (CRA) Address (inaccessible directly from the CPU) • Normal transfer mode Value after reset: • Repeat transfer mode/block transfer mode CRAH CRAL Value after reset: Notes: 1. The function depends on transfer mode. 2.
Page 341: Dtc Transfer Count Register B (Crb)
RX610 Group 13. Data Transfer Controller (DTC) 13.2.6 DTC Transfer Count Register B (CRB) Address (inaccessible directly from the CPU) Value after reset: [Legend] x: Undefined CRB is used to set the block transfer count for block transfer mode. The transfer count is 1, 65535, and 65536 when the set value is 0001h, FFFFh, and 0000h, respectively. The CRB value is decremented (-1) at each data transfer.
Page 342: Dtc Vector Base Register (Dtcvbr)
RX610 Group 13. Data Transfer Controller (DTC) ERR Flag (Transfer Stop Flag) The ERR flag indicates that a DTC transfer stop request is present due to a bus error or nonmaskable interrupt. When the DTC accepts a transfer stop request, it stops data transfer. [Setting condition] •...
Page 343: Dtc Address Mode Register (Dtcadmod)
RX610 Group 13. Data Transfer Controller (DTC) 13.2.9 DTC Address Mode Register (DTCADMOD) Address: 0008 7408h — — — — — — — SHORT Value after reset: Symbol Bit Name Description SHORT Short-Address Mode 0: Full-address mode 1: Short-address mode ...
Page 344: Sources Of Activation
RX610 Group 13. Data Transfer Controller (DTC) 13.3 Sources of Activation The DTC is activated by an interrupt request. Setting ISEL[1:0] bits in an ISELRi register (where i is the interrupt vector number of the given interrupt) of the ICU to 01b selects the corresponding interrupt as an activation source for the DTC, and clearing the same bits to 00b selects the interrupt as a source of interrupts for the CPU.
Page 345 RX610 Group 13. Data Transfer Controller (DTC) Upper: DTCVBR Vector table Lower: Vector number × 4 Transfer data (1) DTC vector address Transfer data (1) start address Transfer data (2) start address Transfer data (2) Transfer data (n) start address 4 bytes Transfer data (n) 4 bytes...
Page 346: Startup Source And Vector Address
RX610 Group 13. Data Transfer Controller (DTC) 13.3.2 Startup source and Vector Address Table 13.3 shows the correspondence between DTC startup sources and vector addresses. Table 13.3 Correspondence between Interrupt Sources, DTC Vector Addresses, and the ISELRi Register of the ICU ISELRi Register of Activation Request Activation Source...
Page 347 RX610 Group 13. Data Transfer Controller (DTC) ISELRi Register of Activation Request Activation Source Vector Number DTC Vector Address Offset the ICU Priority Generation Source TPU5 TGI5A 0214h ISELR133 High TGI5B 0218h ISELR134 TPU6 TGI6A 0228h ISELR138 TGI6B 022Ch ISELR139 TGI6C 0230h ISELR140...
Page 348 RX610 Group 13. Data Transfer Controller (DTC) ISELRi Register of Activation Request Activation Source Vector Number DTC Vector Address Offset the ICU Priority Generation Source SCI6 RXI6 03BCh ISELR239 High TXI6 03C0h ISELR240 RIIC0 RXI0 03DCh ISELR247 TXI0 03E0h ISELR248 RIIC1 RXI1 03ECh...
Page 349: Operation
RX610 Group 13. Data Transfer Controller (DTC) 13.4 Operation The DTC stores transfer data in the data area. When the DTC is activated, it reads the DTC vector corresponding to the vector number. Then the DTC reads transfer data from the transfer data store address pointed by the DTC vector, transfers data, and then writes back the transfer data after the data transfer.
Page 350 RX610 Group 13. Data Transfer Controller (DTC) START Match and RRS bit = 1 Compare vector numbers. Match? Mismatch RRS bit = 0 Read DTC vector Next transfer Read transferred data Transfer data Update transfer data Update transfer data start address Write transfer data CHNE bit = 1? Transfer counter = 0...
Page 351 RX610 Group 13. Data Transfer Controller (DTC) Table 13.5 Chain Transfer Conditions First Transfer Second Transfer CHNE CHNS DISEL Transfer CHNE CHNS DISEL Transfer Counter* Counter* DTC Transfer      Other than 0 Ends after the first transfer ...
Page 352: Transfer Data Read Skip Function
RX610 Group 13. Data Transfer Controller (DTC) 13.4.1 Transfer Data Read Skip Function Vector address read and transfer data read can be skipped by the setting of the RRS bit in DTCCR. When a DTC startup request is generated, the current DTC vector number is always compared with the DTC vector number in the previous startup process.
Page 353: Transfer Data Write-Back Skip Function
RX610 Group 13. Data Transfer Controller (DTC) 13.4.2 Transfer Data Write-Back Skip Function When the SM[1:0] bits in MRA or the DM[1:0] bits in MRB are set to "address fixed", a part of transfer data is not written back. This function is performed independently of the setting of short-address mode or full-address mode. Table 13.6 lists transfer data write-back skip conditions and applicable registers.
Page 354: Normal Transfer Mode
RX610 Group 13. Data Transfer Controller (DTC) 13.4.3 Normal Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single startup source. The transfer count can be set to 1 to 65536. Transfer source addresses and transfer destination addresses can be set to increment, decrement, or fixed independently. This mode enables an interrupt request to the CPU to be generated at the end of specified-count transfer.
Page 355: Repeat Transfer Mode
RX610 Group 13. Data Transfer Controller (DTC) 13.4.4 Repeat Transfer Mode This mode allows 1-byte, 1-word, or 1-longword data transfer on a single startup source. Specify either transfer source or transfer destination for the repeat area by the DTS bit in MRB. The transfer count can be set to 1 to 256.
Page 356 RX610 Group 13. Data Transfer Controller (DTC) Transfer source data area Transfer destination data area (set to repeat area) Data 1 Data 1 Data 2 Transfer Data 2 Data 3 Data 3 Data 4 Data 4 Data 1 Data 2 Data 3 Data 4 Figure 13.7...
Page 357: Block Transfer Mode
RX610 Group 13. Data Transfer Controller (DTC) 13.4.5 Block Transfer Mode This mode allows single-block data transfer on a single startup source. Specify either transfer source or transfer destination for the block area by the DTS bit in MRB. The block size can be set to 1 to 256 bytes (or 1 to 256 words or 1 to 256 longwords).
Page 358: Chain Transfer
RX610 Group 13. Data Transfer Controller (DTC) 13.4.6 Chain Transfer Setting the CHNE bit in MRB to 1 allows multiple data transfers continuously on a single startup source. Chain transfer can be set independently for registers SAR, DAR, CRA, and CRB that define data transfer, as well as for registers MRA and MRB.
Page 359: Operation Timing
RX610 Group 13. Data Transfer Controller (DTC) 13.4.7 Operation Timing Figures 13.10 to 13.13 show examples of DTC operation timing. System clock ICU.IRi Request for DTC activation Access by DTC Reading Transferri Reading the Writing the transfer- ng data transfer- vector control control...
Page 360 RX610 Group 13. Data Transfer Controller (DTC) System clock ICU.IRi Request for DTC activation Access by DTC Reading Reading the Transfer Writting the Reading the Transferri Writting the transfer-control ring transfer- transfer- transfer- vector information data control control data control information information information...
Page 361: Execution Cycle Of The Dtc
RX610 Group 13. Data Transfer Controller (DTC) 13.4.8 Execution Cycle of the DTC Table 13.10 lists the execution cycle of single data transfer of the DTC. Table 13.10 Table 13.10 Execution Cycle of the DTC Transfer Vector Internal Mode Read Transfer Data Read Transfer Data Write Data Read...
Page 362: Dtc Setting Procedure
RX610 Group 13. Data Transfer Controller (DTC) 13.5 DTC Setting Procedure Figure 13.14 shows the procedure to set the DTC. START Set ing the RRS bit in DTCCR to 0 resets the transfer data read skip flag. After that, transfer data read is not skipped while the DTC is Set the RRS bit in DTCCR to 0 activated.
Page 363: Examples Of Dtc Usage
RX610 Group 13. Data Transfer Controller (DTC) 13.6 Examples of DTC Usage 13.6.1 Normal Transfer As an example of DTC usage, its employment in the transfer of 128 bytes of data by an SCI is described below. 1. In the MRA register, make the settings to select a fixed source address (MRA.SM[1:0] = 00b), incrementation of the destination address (MRA.DM[1:0] = 10b), transfer in normal mode (MRA.MD[1:0] = 00b), and byte-sized transfer (MRA.SZ[1:0] = 00b).
Page 364: Chain Transfer
RX610 Group 13. Data Transfer Controller (DTC) 13.6.2 Chain Transfer As an example of chained transfer by the DTC, its employment in the output of pulses by a PPG is described below. Chained transfer is used to transfer pulse output data and vary the period of the output trigger for the PPG. The first half of the chained transfer is in repeated-transfer mode and the destinations for transfer are the PPGm.NDRH and PPGm.NDRL (where m = 0 or 1) registers.
Page 365: Chain Transfer When Counter = 0
RX610 Group 13. Data Transfer Controller (DTC) 13.6.3 Chain Transfer when Counter = 0 The second data transfer is performed only when the counter = 0. Repeat transfer of a transfer count of 256 or more is enabled by the re-setting for the first data transfer. The following shows an example of configuring a 128-kbyte input buffer, where the input buffer is set so that its lower address starts with 0000h.
Page 366 RX610 Group 13. Data Transfer Controller (DTC) Input circuit Transfer data allocated in the on-chip memory space Input buffer First data transfer Chain transfer Transfer data (counter = 0) Second data transfer Transfer data Upper 8 bits of DAR Figure 13.15 Chain Transfer when Counter = 0 R01UH0032EJ0120 Rev.1.20 Page 366 of 1006...
Page 367: Interrupt Source
RX610 Group 13. Data Transfer Controller (DTC) 13.7 Interrupt Source When the DTC has finished data transfer of specified count or when data transfer with the DISEL bit in MRB set to 1 (an interrupt request to the CPU is generated each time DTC data transfer is performed) has been completed, an interrupt to the CPU is generated by the DTC startup source.
Page 368: Allocating Transfer Data
RX610 Group 13. Data Transfer Controller (DTC) 13.9.2 Allocating Transfer Data Allocate transfer data in the memory area according to the endian of the area as shown in figure 13.16. For example, when writing CRA and CRB setting data with 16 bits in big endian, write the CRA setting data to lower address 0 and the CRB setting data to lower address 2.
Page 369: Overview
RX610 Group 14. I/O Ports I/O Ports The I/O ports of the RX610 Group function as a programmable I/O port, an I/O pin of a peripheral module, an input pin for an interrupt, or a bus control pin. Each pin is also configurable as an I/O pin of a peripheral module or an input pin for an interrupt. All pins function as input pins immediately after a reset, and pin functions are switched by register settings.
Page 370 RX610 Group 14. I/O Ports Table 14.2 Port Functions Input Function Pull-up Open Drain CMOS Schmitt Trigger Resistor Output Port Description Input Output Input Input Function Capability    Port 0 General I/O port TMRI2/IRQ8-A TxD6 All input functions pins, on-chip TMCI2/RxD6/ All input functions...
Page 371 RX610 Group 14. I/O Ports Input Function Pull-up Open Drain CMOS Schmitt Trigger Resistor Output Port Description Input Output Input Input Function Capability    Port 3 General I/O port P30/TIOCA0 IRQ0-A All input functions pins, interrupt P31/TIOCB0 TIOCA0/IRQ1-A All input functions inputs, TPU I/O P32/TIOCC0...
Page 372 RX610 Group 14. I/O Ports    Port 7 General I/O port ADTRG2# CS3#-B All input functions pins, interrupt CS4#-C/ All input functions inputs, bus control CS5#-C/ outputs, and A/D CS6#-C/ converter inputs CS7#-C All input functions All input functions ADTRG3# All input functions All input functions...
Page 373 RX610 Group 14. I/O Ports   √ Port B General I/O port PB0/TIOCA9 A8/PO24 All input functions pins, address PB1/TIOCB9 TIOCA9 A9/PO25 All input functions outputs, TPU I/O PB2/TIOCC9 A10/PO26 All input functions signals, and PPG PB3/TIOCD9 TIOCC9 A11/PO27 All input functions outputs PB4/TIOCA10...
Page 374 RX610 Group 14. I/O Ports    Port F General I/O port All input functions pins All input functions All input functions All input functions All input functions All input functions All input functions    Port G General I/O port All input functions pins...
Page 375: Register Descriptions
RX610 Group 14. I/O Ports 14.2 Register Descriptions Table 14.3 lists registers of each port. Table 14.3 Registers for Each Port Value after Port Symbol Register Name Register Symbol Reset Address Access Size Data direction register 0008 C000h Data register 0008 C020h Port register PORT...
Page 376 RX610 Group 14. I/O Ports Value after Port Symbol Register Name Register Symbol Reset Address Access Size Data direction register 0008 C009h Data register 0008 C029h Port register PORT Undefined 0008 C049h Input buffer control register 0008 C069h Data direction register 0008 C00Ah Data register 0008 C02Ah...
Page 377 RX610 Group 14. I/O Ports Value after Port Symbol Register Name Register Symbol Reset Address Access Size Common to Port function control register 0 PFCR0 0008 C100h two or more Port function control register 1 PFCR1 0008 C101h ports Port function control register 2 PFCR2 0008 C102h Port function control register 3...
Page 378: Data Direction Register (Ddr)
RX610 Group 14. I/O Ports 14.2.1 Data Direction Register (DDR) Addresses: P0.DDR 0008 C000h, P1.DDR 0008 C001h, P2.DDR 0008 C002h, P3.DDR 0008 C003h, P4.DDR 0008 C004h, P5.DDR0008 C005h, P6.DDR 0008 C006h, P7.DDR 0008 C007h, P8.DDR 0008 C008h, P9.DDR 0008 C009h, PA.DDR 0008 C00Ah, PB.DDR 0008 C00Bh, PC.DDR 0008 C00Ch, PD.DDR 0008 C00Dh, PE.DDR 0008 C00Eh, PF.DDR 0008 C00Fh, PG.DDR 0008 C010h, PH.DDR 0008 C011h Value after reset:...
Page 379: Data Register (Dr)
RX610 Group 14. I/O Ports 14.2.2 Data Register (DR) Addresses: P0.DR 0008 C020h, P1.DR 0008 C021h, P2.DR 0008 C022h, P3.DR 0008 C023h, P4.DR 0008 C024h, P5.DR 0008 C025h, P6.DR 0008 C026h, P7.DR 0008 C027h, P8.DR 0008 C028h, P9.DR 0008 C029h, PA.DR 0008 C02Ah, PB.DR 0008 C02Bh, PC.DR 0008 C02Ch, PD.DR 0008 C02Dh, PE.DR 0008 C02Eh, PF.DR 0008 C02Fh, PG.DR 0008 C030h, PH.DR 0008 C031h Value after reset:...
Page 380: Port Register (Port)
RX610 Group 14. I/O Ports 14.2.3 Port Register (PORT) Addresses: P0.PORT 0008 C040h, P1.PORT 0008 C041h, P2.PORT 0008 C042h, P3.PORT 0008 C043h, P4.PORT 0008 C044h, P5.PORT 0008 C045h, P6.PORT 0008 C046h, P7.PORT 0008 C047h, P8.PORT0008 C048h, P9.PORT 0008 C049h, PA.PORT 0008 C04Ah, PB.PORT 0008 C04Bh, PC.PORT 0008 C04Ch, PD.PORT 0008 C04Dh, PE.PORT 0008 C04Eh, PF.PORT 0008 C04Fh, PG.PORT 0008 C050h, PH.PORT 0008 C051h Value after reset:...
Page 381: Input Buffer Control Register (Icr)
RX610 Group 14. I/O Ports 14.2.4 Input Buffer Control Register (ICR) Addresses: P0.ICR 0008 C060h, P1.ICR 0008 C061h, P2.ICR 0008 C062h, P3.ICR 0008 C063h, P4.ICR 0008 C064h, P5.ICR 0008 C065h, P6.ICR 0008 C066h, P7.ICR 0008 C067h, P8.ICR 0008 C068h, P9.ICR 0008 C069h, PA.ICR 0008 C06Ah, PB.ICR 0008 C06Bh, PC.ICR 0008 C06Ch, PD.ICR 0008 C06Dh, PE.ICR 0008 C06Eh, PF.ICR 0008 C06Fh, PG.ICR 0008 C070h, PH.ICR 0008 C071h Value after reset:...
Page 382: Pull-Up Resistor Control Register (Pcr)
RX610 Group 14. I/O Ports 14.2.5 Pull-Up Resistor Control Register (PCR) Addresses: PA.PCR 0008 C0CAh, PB.PCR 0008 C0CBh, PC.PCR 0008 C0CCh, PD.PCR 0008 C0CDh, PE.PCR 0008 C0CEh Value after reset: Symbol Bit Name Description Pm0 Input Pull-Up Resistor Control (m = A to E) 0: Input pull-up resistor is disabled.
Page 383: Open Drain Control Register (Odr)
RX610 Group 14. I/O Ports 14.2.6 Open Drain Control Register (ODR) Addresses: P2.ODR 0008 C082h, PC.ODR 0008 C08Ch Value after reset: Symbol Bit Name Description Pm0 Output Type Select (m = 2 and C) 0: CMOS output pin 1: NMOS open-drain output pin Pm1 Output Type Select Pm2 Output Type Select Pm3 Output Type Select...
Page 384: Port Function Control Register 1 (Pfcr1)
RX610 Group 14. I/O Ports 14.2.8 Port Function Control Register 1 (PFCR1) Address: 0008 C101h CS7S[1:0] CS6S[1:0] CS5S[1:0] CS4S[1:0] Value after reset: Symbol Bit Name Description b1 b0 b1, b0 CS4S[1:0] CS4# Output Pin Select 0: CS4#-A is output from P60. 1: CS4#-B is output from P64.
Page 385 RX610 Group 14. I/O Ports Figure 14.1 describes the timing for output of CSn# signals for CS5 and CS6 areas to the same pin. Table 14.5 lists the relationship between CS# output pin select registers and output pins. Access to CS5 area Idle cycle Access to CS6 area BCLK...
Page 386: Port Function Control Register 2 (Pfcr2)
RX610 Group 14. I/O Ports 14.2.9 Port Function Control Register 2 (PFCR2) Address: 0008 C102h — — — — — — CS3S CS2S Value after reset: Symbol Bit Name Description  b5 to b0 Reserved These bits are read as 0. The write value should be 0.
Page 387: Port Function Control Register 3 (Pfcr3)
RX610 Group 14. I/O Ports 14.2.10 Port Function Control Register 3 (PFCR3) Address: 0008 C103h A23E A22E A21E A20E A19E A18E A17E A16E Value after reset: Symbol Bit Name Description A16E Address A16 Enable 0: A16 output is disabled. 1: A16 output is enabled. A17E Address A17 Enable 0: A17 output is disabled.
Page 388: Port Function Control Register 4 (Pfcr4)
RX610 Group 14. I/O Ports 14.2.11 Port Function Control Register 4 (PFCR4) Address: 0008 C104h A15E A14E A13E A12E A11E A10E Value after reset: Symbol Bit Name Description Address A8 Enable 0: A8 output is disabled. 1: A8 output is enabled. Address A9 Enable 0: A9 output is disabled.
Page 389: Port Function Control Register 5 (Pfcr5)
RX610 Group 14. I/O Ports 14.2.12 Port Function Control Register 5 (PFCR5) Address: 0008 C105h — — — — — WR1BC1E TCLKS Value after reset: Symbol Bit Name Description  b2 to b0 Reserved These bits are read as 0. The write value should be 0. TCLKS TPU External Clock 0: P32, P33, P35, and P37 are designated as external clock...
Page 390: Port Function Control Register 6 (Pfcr6)
RX610 Group 14. I/O Ports 14.2.13 Port Function Control Register 6 (PFCR6) Address: 0008 C106h TPUMS5 TPUMS4 TPUMS3A TPUMS3B TPUMS2 TPUMS1 TPUMS0A TPUMS0B Value after reset: Symbol Bit Name Description TPUMS0B Multifunction Select 0B 0: Output compare and input capture are allocated to P32. for TPU I/O Pins 1: Input capture and output compare are allocated to P33 and P32, respectively.
Page 391 RX610 Group 14. I/O Ports TPUMS0A Bit (Multifunction Select 0A for TPU I/O Pins) This bit selects an input pin for TIOCA0. TPUMS1 Bit (Multifunction Select 1 for TPU I/O Pins) This bit selects an input pin for TIOCA1. TPUMS2 Bit (Multifunction Select 2 for TPU I/O Pins) This bit selects an input pin for TIOCA2.
Page 392 RX610 Group 14. I/O Ports TPU2.TGRA TPU2.TGRB TPU2.TMDR. PFCR6. Input Capture Input Capture ICSELB TPUMS2 Input External Pin Input External Pin TIOCB2 TIOCB2 TIOCA2 TIOCA2 TIOCA2 TPU3.TGRC TPU3.TGRD TPU3.TMDR. PFCR6. Input Capture Input Capture ICSELD TPUMS3B Input External Pin Input External Pin TIOCC3 TIOCD3...
Page 393: Port Function Control Register 7 (Pfcr7)
RX610 Group 14. I/O Ports 14.2.14 Port Function Control Register 7 (PFCR7) Address: 0008 C107h TPUMS11 TPUMS10 TPUMS9A TPUMS9B TPUMS8 TPUMS7 TPUMS6A TPUMS6B Value after reset: Symbol Bit Name Description TPUMS6B Multifunction Select 6B 0: Output compare and input capture are allocated to PA2. for TPU I/O Pins 1: Input capture and output compare are allocated to PA3 and PA2, respectively.
Page 394 RX610 Group 14. I/O Ports TPUMS6A Bit (Multifunction Select 6A for TPU I/O Pins) This bit selects an input pin for TIOCA6. TPUMS7 Bit (Multifunction Select 7 for TPU I/O Pins) This bit selects an input pin for TIOCA7. TPUMS8 Bit (Multifunction Select 8 for TPU I/O Pins) This bit selects an input pin for TIOCA8.
Page 395 RX610 Group 14. I/O Ports TPU8.TGRA TPU8.TGRB TPU8.TMDR. PFCR7. Input Capture Input Capture ICSELB TPUMS8 Input External Pin Input External Pin TIOCA8 TIOCB8 TIOCB8 TIOCA8 TIOCA8 TPU9.TGRC TPU9.TGRD TPU9.TMDR. PFCR7. Input Capture Input Capture ICSELD TPUMS9B Input External Pin Input External Pin TIOCC9 TIOCD9...
Page 396: Port Function Control Register 8 (Pfcr8)
RX610 Group 14. I/O Ports 14.2.15 Port Function Control Register 8 (PFCR8) Address: 0008 C108h ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 Value after reset: Symbol Bit Name Description ITS8 IRQ8 Pin Select 0: P00 is designated as the IRQ8-A input pin. 1: P40 is designated as the IRQ8-B input pin.
Page 397: Port Function Control Register 9 (Pfcr9)
RX610 Group 14. I/O Ports 14.2.16 Port Function Control Register 9 (PFCR9) Address: 0008 C109h ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 Value after reset: Symbol Bit Name Description ITS0 IRQ0 Pin Select 0: P30 is designated as the IRQ0-A input pin. 1: P10 is designated as the IRQ0-B input pin.
Page 398: Settings Of Ports
RX610 Group 14. I/O Ports 14.3 Settings of Ports Individual pins for peripheral modules are indicated by "_OE" appended to the end of the pin name (for example, TIOCA4_OE). In addition, the settings to enable desired outputs and the other settings are indicated as 1 and 0 in the following tables, respectively.
Page 399 RX610 Group 14. I/O Ports (3) P02/TMO2/SCK6/(IRQ10-A)/(TRST#) The pin function is switched as shown below according to the combination of the register settings for the TMR and SCI and the B2 bit in P0.DDR. Setting I/O Port Module Name Pin Function TMO2_OE SCK6_OE P0.DDR.B2...
Page 400: Port 1 (P1)
RX610 Group 14. I/O Ports 14.3.2 Port 1 (P1) (1) P10/(IRQ0-B) The pin function is switched as shown below according to the value of the B0 bit in P1.DDR. Setting I/O Port Module Name Pin Function P1.DDR.B0 I/O port P10 output P10 input (initial value) (2) P11/SCK2/(IRQ1-B) The pin function is switched as shown below according to the combination of the register setting for the SCI and the B1...
Page 401 RX610 Group 14. I/O Ports (5) P14/(TCLKA-B)/SDA1/(IRQ4-B) The pin function is switched as shown below according to the combination of the register setting for the RIIC and the B4 bit in P1.DDR. Setting RIIC I/O Port Module Name Pin Function SDA1_OE P1.DDR.B4 ...
Page 402: Port 2 (P2)
RX610 Group 14. I/O Ports 14.3.3 Port 2 (P2) (1) P20/PO0/(TIOCA3)/TIOCB3/(TMRI0)/TxD0 The pin function is switched as shown below according to the combination of the register settings for the TPU, SCI, and PPG, and the B0 bit in P2.DDR. Setting I/O Port TIOCB3_OE TxD0_OE...
Page 403 RX610 Group 14. I/O Ports (4) P23/PO3/(TIOCC3)/TIOCD3 The pin function is switched as shown below according to the combination of the register settings for the TPU and PPG, and the B3 bit in P2.DDR. Setting I/O Port Module Name Pin Function TIOCD3_OE PO3_OE P2.DDR.B3...
Page 404 RX610 Group 14. I/O Ports (7) P26/PO6/TIOCA5/TMO1/TxD1 The pin function is switched as shown below according to the combination of the register settings for the TPU, TMR , SCI, and PPG, and the B6 bit in P2.DDR. Setting I/O Port Module Name Pin Function TIOCA5_OE...
Page 405: Port 3 (P3)
RX610 Group 14. I/O Ports 14.3.4 Port 3 (P3) (1) P30/PO8/TIOCA0/(IRQ0-A) The pin function is switched as shown below according to the combination of the register settings for the TPU and PPG, and the B0 bit in P3.DDR. Setting I/O Port Module Name Pin Function TIOCA0_OE...
Page 406 RX610 Group 14. I/O Ports (4) P33/PO11/(TIOCC0)/TIOCD0/(TCLKB-A)/(IRQ3-A) The pin function is switched as shown below according to the combination of the register settings for the TPU and PPG, and the B3 bit in P3.DDR. Setting I/O Port Module Name Pin Function TIOCD0_OE PO11_OE P3.DDR.B3...
Page 407 RX610 Group 14. I/O Ports (7) P36/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the register settings for the TPU and PPG, and the B6 bit in P3.DDR. Setting I/O Port Module Name Pin Function TIOCA2_OE PO14_OE P3.DDR.B6...
Page 408: Port 4 (P4)
RX610 Group 14. I/O Ports 14.3.5 Port 4 (P4) (1) P40/(AN0)/(IRQ8-B) The pin function is switched as shown below according to the value of the B0 bit in P4.DDR. Setting I/O Port Module Name Pin Function P4.DDR.B0 I/O port P40 output P40 input (initial value) (2) P41/(AN1)/(IRQ9-B) The pin function is switched as shown below according to the value of the B1 bit in P4.DDR.
Page 409 RX610 Group 14. I/O Ports (5) P44/(AN4)/(IRQ12-B) The pin function is switched as shown below according to the value of the B4 bit in P4.DDR. Setting I/O Port Module Name Pin Function P4.DDR.B4 I/O port P44 output P44 input (initial value) (6) P45/(AN5)/(IRQ13-B) The pin function is switched as shown below according to the value of the B5 bit in P4.DDR.
Page 410: Port 5 (P5)
RX610 Group 14. I/O Ports 14.3.6 Port 5 (P5) (1) P50/WR0#/WR# The pin function is switched as shown below according to the combination of the register setting for the bus controller and the B0 bit in P5.DDR. Setting Bus Controller I/O Port Module Name Pin Function...
Page 411 RX610 Group 14. I/O Ports (4) P53/BCLK The pin function is switched as shown below according to the value of the B3 bit in P5.DDR. Setting I/O Port Module Name Pin Function P5.DDR.B3 (BCLK_OE) Clock generation circuit BCLK output I/O port P53 input (initial value) Note: If the BCLK signal is to be output, stop the BCLK clock by setting SCKCR.PSTOP1 to 1, set P5.DDR.B3 to select output for this pin, and then restore the value of SCKCR.PSTOP1 to 1 for output of the BCLK signal.
Page 412: Port 6 (P6)
RX610 Group 14. I/O Ports 14.3.7 Port 6 (P6) (1) P60/CS0#/CS4#-A/CS5#-B The pin function is switched as shown below according to the combination of the operating mode, the external bus enable bit (EXBE) in the system control register 0 (SYSCR0), the register setting for the bus controller, the port function control register m (PFCRm) setting, and the B0 bit in P6.DDR.
Page 413 RX610 Group 14. I/O Ports (3) P62/CS2#-A/CS6#-A The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0, the register setting for the bus controller, the port function control register m (PFCRm) setting, and the B2 bit in P6.DDR. Setting Bus Controller I/O Port...
Page 414 RX610 Group 14. I/O Ports (6) P65/(IRQ15-A) The pin function is switched as shown below according to the value of the B5 bit in P6.DDR. Setting I/O Port Module Name Pin Function P6.DDR.B5 I/O port P65 output P65 input (initial value) (7) P66/DA0 The pin function is switched as shown below according to the register setting for the D/A converter and the B6 bit in P6.DDR.
Page 415: Port 7 (P7)
RX610 Group 14. I/O Ports 14.3.8 Port 7 (P7) (1) P70/CS3#-B/(ADTRG2#) The pin function is switched as shown below according to the combination of the external bus enable bit (EXBE) in the system control register 0 (SYSCR0), the rgister setting for the bus controller, the port function control register m (PFCRm) setting, and the B0 bit in P7.DDR.
Page 416 RX610 Group 14. I/O Ports (4) P73 The pin function is switched as shown below according to the value of the B3 bit in P7.DDR. Setting I/O Port Module Name Pin Function P7.DDR.B3 I/O port P73 output P73 input (initial value) (5) P74/(ADTRG3#) The pin function is switched as shown below according to the value of the B4 bit in P7.DDR.
Page 417: Port 8 (P8)
RX610 Group 14. I/O Ports 14.3.9 Port 8 (P8) (1) P80 The pin function is switched as shown below according to the value of the B0 bit in P8.DDR. Setting I/O Port Module Name Pin Function P8.DDR.B0 I/O port P80 output P80 input (initial value) (2) P81/TRSYNC# The pin function is switched as shown below according to the value of the B1 bit in P8.DDR.
Page 418 RX610 Group 14. I/O Ports (5) P84 The pin function is switched as shown below according to the value of the B4 bit in P8.DDR. Setting I/O Port Module Name Pin Function P8.DDR.B4 I/O port P84 output P84 input (initial value) (6) P85 The pin function is switched as shown below according to the value of the B5 bit in P8.DDR.
Page 419: Port 9 (P9)
RX610 Group 14. I/O Ports 14.3.10 Port 9 (P9) (1) P90/(AN8) The pin function is switched as shown below according to the value of the B0 bit in P9.DDR. Setting I/O Port Module Name Pin Function P9.DDR.B0 I/O port P90 output P90 input (initial value) (2) P91/(AN9) The pin function is switched as shown below according to the value of the B1 bit in P9.DDR.
Page 420 RX610 Group 14. I/O Ports (5) P94/(AN12) The pin function is switched as shown below according to the value of the B4 bit in P9.DDR. Setting I/O Port Module Name Pin Function P9.DDR.B4 I/O port P94 output P94 input (initial value) (6) P95/(AN13) The pin function is switched as shown below according to the value of the B5 bit in P9.DDR.
Page 421: Port A (Pa)
RX610 Group 14. I/O Ports 14.3.11 Port A (PA) (1) PA0/A0/BC0#/PO16/TIOCA6 The pin function is switched as shown below according to the combination of the external bus enable bit (EXBE) in the system control register 0 (SYSCR0), the rgister settings for the PPG and TPU, and the B0 bit in PA.DDR. Setting Bus Controller I/O Port...
Page 422 RX610 Group 14. I/O Ports (3) PA2/A2/PO18/TIOCC6/(TCLKE) The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0, the rgister settings for the PPG and TPU, and the B2 bit in PA.DDR. Setting Bus Controller I/O Port PO18_OE...
Page 423 RX610 Group 14. I/O Ports (5) PA4/A4/PO20/TIOCA7 The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0, the rgister settings for the PPG and TPU, and the B4 bit in PA.DDR. Setting Bus Controller I/O Port PO20_OE...
Page 424 RX610 Group 14. I/O Ports (7) PA6/A6/PO22/TIOCA8 The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0, the rgister settings for the PPG and TPU, and the B6 bit in PA.DDR. Setting Bus Controller I/O Port PO22_OE...
Page 425: Port B (Pb)
RX610 Group 14. I/O Ports 14.3.12 Port B (PB) (1) PB0/A8/PO24/TIOCA9 The pin function is switched as shown below according to the combination of the external bus enable bit (EXBE) in the system control register 0 (SYSCR0), the rgister settings for the PPG and TPU, the port function control register m (PFCRm) setting, and the B0 bit in PB.DDR.
Page 426 RX610 Group 14. I/O Ports (3) PB2/A10/PO26/TIOCC9 The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0, the rgister settings for the PPG and TPU, the port function control register m (PFCRm) setting, and the B2 bit in PB.DDR. Setting Bus Controller I/O Port...
Page 427 RX610 Group 14. I/O Ports (6) PB5/A13/PO29/(TIOCA10)/TIOCB10 The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0, the rgister settings for the PPG and TPU, the port function control register m (PFCRm) setting, and the B5 bit in PB.DDR. Setting Bus Controller I/O Port...
Page 428: Port C (Pc)
RX610 Group 14. I/O Ports 14.3.13 Port C (PC) (1) PC0/A16 The pin function is switched as shown below according to the combination of the external bus enable bit (EXBE) in the system control register 0 (SYSCR0), the register setting for the bus controller, the port function control register m (PFCRm) setting, and the B0 bit in PC.DDR Setting Bus Controller...
Page 429 RX610 Group 14. I/O Ports (4) PC3/A19 The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0, the rgister setting for the bus controller, the port function control register m (PFCRm) setting, and the B3 bit in PC.DDR. Setting Bus Controller I/O Port...
Page 430 RX610 Group 14. I/O Ports (7) PC6/A22/(RxD5)/CS6#-D The pin function is switched as shown below according to the combination of the EXBE bit in SYSCR0, the rgister setting for the bus controller, the port function control register m (PFCRm) setting, and the B6 bit in PC.DDR. Setting Bus Controller I/O Port...
Page 431: Port D (Pd)
RX610 Group 14. I/O Ports 14.3.14 Port D (PD) (1) PD0/D0, PD1/D1, PD2/D2, PD3/D3, PD4/D4, PD5/D5, PD6/D6, PD7/D7 The pin function is switched as shown below according to the combination of the external bus enable (EXBE) bit in the system control register 0 (SYSCR0) and the Bj bit (j = 0 to 7) in PD.DDR. Setting I/O Port Module Name...
Page 432: Port F (Pf)
RX610 Group 14. I/O Ports 14.3.16 Port F (PF) (1) PF0 The pin function is switched as shown below according to the value of the B0 bit in PF.DDR. Setting I/O Port Module Name Pin Function PF.DDR.B0 I/O port PF0 output PF0 input (initial value) (2) PF1 The pin function is switched as shown below according to the value of the B1 bit in PF.DDR.
Page 433 RX610 Group 14. I/O Ports (5) PF4 The pin function is switched as shown below according to the value of the B4 bit in PF.DDR. Setting I/O Port Module Name Pin Function PF.DDR.B4 I/O port PF4 output PF4 input (initial value) (6) PF5 The pin function is switched as shown below according to the value of the B5 bit in PF.DDR.
Page 434: Port G (Pg)
RX610 Group 14. I/O Ports 14.3.17 Port G (PG) (1) PG0 The pin function is switched as shown below according to the value of the B0 bit in PG.DDR. Setting I/O Port Module Name Pin Function PG.DDR.B0 I/O port PG0 output PG0 input (initial value) (2) PG1 The pin function is switched as shown below according to the value of the B1 bit in PG.DDR.
Page 435 RX610 Group 14. I/O Ports (6) PG5 The pin function is switched as shown below according to the value of the B5 bit in PG.DDR. Setting I/O Port Module Name Pin Function PG.DDR.B5 I/O port PG5 output PG5 input (initial value) (7) PG6 The pin function is switched as shown below according to the value of the B6 bit in PG.DDR.
Page 436: Port H (Ph)
RX610 Group 14. I/O Ports 14.3.18 Port H (PH) (1) PH0 The pin function is switched as shown below according to the value of the B0 bit in PH.DDR. Setting I/O Port Module Name Pin Function PH.DDR.B0 I/O port PH0 output PH0 input (initial value) (2) PH1 The pin function is switched as shown below according to the value of the B1 bit in PH.DDR.
Page 437 RX610 Group 14. I/O Ports (6) PH5 The pin function is switched as shown below according to the value of the B5 bit in PH.DDR. Setting I/O Port Module Name Pin Function PH.DDR.B5 I/O port PH5 output PH5 input (initial value) (7) PH6 The pin function is switched as shown below according to the value of the B6 bit in PH.DDR.
Page 438: Settings To Enable Output Of The Signals
RX610 Group 14. I/O Ports 14.4 Settings to Enable Output of the Signals Table 14.8 lists the settings to enable output from the individual pins of each port. Table 14.8 Settings to Enable Output of the Signals from Each Port Corresponding Signal Name Output...
Page 439 RX610 Group 14. I/O Ports Corresponding Signal Name Output Register Setting Peripheral for Setting Signal for Selection of Port Module Output Name Signals Setting for Each Internal Module TPU3 TIOCB3_OE TIOCB3 TIORH.IOB[3] = 0, TIORH.IOB[1 0] = 01/10/11 SCI0 TxD0_OE TxD0 SCR.TE = 1 PPG0...
Page 440 RX610 Group 14. I/O Ports Corresponding Signal Name Output Register Setting Peripheral for Setting Signal for Selection of Port Module Output Name Signals Setting for Each Internal Module TPU0 TIOCA0_OE TIOCA0 TIORH.IOA[3] = 0, TIOH.IOA[1:0] = 01/10/11 PPG0 PO8_OE NDERH.NDER8 = 1 TPU0 TIOCB0_OE TIOCB0...
Page 441 RX610 Group 14. I/O Ports Corresponding Signal Name Output Register Setting Peripheral for Setting Signal for Selection of Port Module Output Name Signals Setting for Each Internal Module SYSC CS0_OE SYSCR0.EXBE = 1, PFCR0.CS0E = 1, CS0CNT.EXENB = 1 SYSC CS4A_OE PFCR1.CS4S[1:0] SYSCR0.EXBE = 1, PFCR0.CS4E = 1, CS4CNT.EXENB = 1...
Page 442 RX610 Group 14. I/O Ports Corresponding Signal Name Output Register Setting Peripheral for Setting Signal for Selection of Port Module Output Name Signals Setting for Each Internal Module TPU6 TIOCA6_OE TIOCA6 TIORH.IOA[3] = 0, TIORH.IOA[1:0] = 01/10/11 PPG1 PO 16_OE PO16 NDERL.NDER16 = 1 SYSC,BSC...
Page 443 RX610 Group 14. I/O Ports Corresponding Signal Name Output Register Setting Peripheral for Setting Signal for Selection of Port Module Output Name Signals Setting for Each Internal Module TPU9 TIOCA9_OE TIOCA9 TIORH.IOA[3] = 0, TIORH.IOA[1:0] = 01/10/11 PPG1 PO24_OE PO24 NDERH.NDER24 = 1 SYSC A8_OE...
Page 444 RX610 Group 14. I/O Ports Corresponding Signal Name Output Register Setting Peripheral for Setting Signal for Selection of Port Module Output Name Signals Setting for Each Internal Module SYSC A16_OE SYSCR0.EXBE = 1, PFCR3 A16E = 1 SYSC A17_OE SYSCR0.EXBE = 1, PFCR3.A17E = 1 SYSC A18_OE SYSCR0.EXBE = 1, PFCR3.A18E = 1...
Page 445 RX610 Group 14. I/O Ports Table 14.9 Pin Functions in Each Operating Mode Selection of Operating b7 to b7 to b7 to Modes Operating Mode Selection by Boot mode P*/C the mode pins User boot mode P*/C Single-chip mode P*/C Transition by Single-chip mode the register...
Page 446: Treatment Of Unused Pins
RX610 Group 14. I/O Ports 14.5 Treatment of Unused Pins The treatment of unused pins is listed in table 14.10. Table 14.10 Treatment of Unused Pins Expansion Mode with Expansion Mode with On-Chip ROM Disabled On-Chip ROM Disabled Expansion Mode with Pin Name (16-Bit Bus Width) (8-Bit Bus Width)
Page 447: I/O Port Configuration
RX610 Group 14. I/O Ports 14.6 I/O Port Configuration Port 0: P00 to P05 Port 1: P10 to P17 Port 3: P30 to P37 Port 5: P50 to P52 and P54 to Port 6: P60 to P65 Port 7: P70 to P77 Port 8: P80 to P86 Port F: PF0 to PF6*1 Port G: PG0 to PG7*1...
Page 448 RX610 Group 14. I/O Ports Port 4: P40 to P47 Port 9: P90 to P97 Peripheral module input signal Port read input signal Port read signal AD input enable signal Analog input Port 5: P53 BCLK output signal Port read input signal Port read signal Figure 14.3 I/O Port Configuration (2) R01UH0032EJ0120 Rev.1.20...
Page 449 RX610 Group 14. I/O Ports Port 6: P66 and P67 Port read input signal Port read signal DA output enable signal Analog output Port A: PA0 to PA7 Port B: PB0 to PB7 Peripheral module output signal Enabling a peripheral module output Peripheral module input signal Port read input signal...
Page 450 RX610 Group 14. I/O Ports Port C: PC0 to PC7 Peripheral module output signal Enabling a peripheral module output Peripheral module input signal Port read input signal Port read signal Port D: PD0 to PD7 Port E: PE0 to PE7 Peripheral module output signal Port read input signal Port read signal...
Page 451: Usage Notes
RX610 Group 14. I/O Ports 14.7 Usage Notes 14.7.1 Setting the Input Buffer Control Register (Pm.ICR) Changes to Pm.ICR settings can lead to the generation of internal edges, depending on the setting and the pin states at the time it is made. Change the setting of a Pm.ICR while the input signal from the pins is fixed to the high level or, if a peripheral function has been assigned to a pin, while the input function is disabled.
Page 452: Overview
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 16-Bit Timer Pulse Unit (TPU) The RX610 Group has two on-chip 16-bit timer pulse units (TPU), unit 0 and unit 1, each comprising six channels. Therefore, this LSI includes twelve channels (TPU0 to TPU11). 15.1 Overview Specifications of the TPU are shown in table 15.1.
Page 453 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.2 TPU (Unit 0) Functions Item TPU0 TPU1 TPU2 TPU3 TPU4 TPU5 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/64 PCLK/64...
Page 454 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) DMAC activation TGRA TGRA TGRA TGRA TGRA TGRA compare match or compare match or compare match or compare match or compare match or compare match or input capture input capture input capture input capture input capture input capture...
Page 455 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.3 TPU (Unit 1) Functions Item TPU6 TPU7 TPU8 TPU9 TPU10 TPU11 Count clock PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/1 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/4 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/16 PCLK/64 PCLK/64...
Page 456 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) DMAC activation TGRA TGRA TGRA TGRA TGRA TGRA compare match or compare match or compare match or compare match or compare match or compare match or input capture input capture input capture input capture input capture input capture...
Page 457 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) [Interrupt request signals] [Input/output pins] TPU3: TGI3A TPU3: TIOCA3 TGI3B TIOCB3 TGI3C TIOCC3 TGI3D TIOCD3 TCI3V TPU4: TIOCA4 TPU4: TGI4A TIOCB4 TGI4B TPU5: TIOCA5 TCI4V TIOCB5 TCI4U TPU5: TGI5A TGI5B TCI5V TCI5U [Clock input] Internal clock: PCLK/1...
Page 458 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) [Interrupt request signals] [Input/output pins] TPU9: TGI9A TPU9: TIOCA9 TGI9B TIOCB9 TGI9C TIOCC9 TGI9D TIOCD9 TCI9V TPU10: TIOCA10 TPU10: TGI10A TIOCB10 TGI10B TPU11: TIOCA11 TCI10V TIOCB11 TCI10U TPU11: TGI11A TGI11B TCI11V TCI11U [Clock input] Internal clock: PCLK/1...
Page 459 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.4 lists the input/output pins of the TPU. Table 15.4 Pin Configuration of TPU Unit Channel Pin Name I/O Description Unit 0 TCLKA Input External clock A input pin (TPU1 and TPU5 phase counting mode A phase input) TCLKB Input External clock B input pin (TPU1 and TPU5 phase counting mode B phase input)
Page 460: Register Descriptions
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2 Register Descriptions Table 15.5 lists the registers of the TPU. Table 15.5 Registers of TPU Unit Channel Register Name Symbol Value after Reset Address Access Size Unit 0 TPU0 Timer control register 0008 8110h Timer mode register TMDR...
Page 461 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Unit Channel Register Name Symbol Value after Reset Address Access Size Unit 0 TPU4 Timer control register 0008 8150h Timer mode register TMDR 0008 8151h Timer I/O control register TIOR 0008 8152h Timer interrupt enable register TIER 0008 8154h...
Page 462 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Unit Channel Register Name Symbol Value after Reset Address Access Size Unit 1 TPU8 Timer control register 0008 81A0h Timer mode register TMDR 0008 81A1h Timer I/O control register TIOR 0008 81A2h Timer interrupt enable register TIER 0008 81A4h...
Page 463: Timer Control Register (Tcr)
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2.1 Timer Control Register (TCR) Addresses: TPU0.TCR 0008 8110h, TPU1.TCR 0008 8120h, TPU2.TCR 0008 8130h TPU3.TCR 0008 8140h, TPU4.TCR 0008 8150h, TPU5.TCR 0008 8160h TPU6.TCR 0008 8180h, TPU7.TCR 0008 8190h, TPU8.TCR 0008 81A0h TPU9.TCR 0008 81B0h, TPU10.TCR 0008 81C0h, TPU11.TCR 0008 81D0h CCLR[2:0] CKEG[1:0]...
Page 464 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.6 Bits TPSC[2:0] (TPU0, TPU6) Bits TPSC[2:0] Channel Description TPU0 (unit 0) Internal clock: counts on PCLK/1 TPU6 (unit 1) Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock: counts on TCLKA or TCLKE pin input External clock: counts on TCLKB or TCLKF pin input External clock: counts on TCLKC or TCLKG pin input...
Page 465 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.9 Bits TPSC[2:0] (TPU3, TPU9) Bits TPSC[2:0] Channel Description TPU3 (unit 0) Internal clock: counts on PCLK/1 TPU9 (unit 1) Internal clock: counts on PCLK/4 Internal clock: counts on PCLK/16 Internal clock: counts on PCLK/64 External clock: counts on TCLKA or TCLKE pin input Internal clock: counts on PCLK/1024 Internal clock: counts on PCLK/256...
Page 466 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.12 Bits CKEG[1:0] Bits CKEG[1:0] Input Clock Internal Clock External clock Counted at falling edge Counted at rising edge Counted at rising edge Counted at falling edge Counted at both edges Counted at both edges Counted at both edges Counted at both edges...
Page 467: Timer Mode Register (Tmdr)
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2.2 Timer Mode Register (TMDR) Addresses: TPU0.TMDR 0008 8111h, TPU1.TMDR 0008 8121h, TPU2.TMDR 0008 8131h TPU3.TMDR 0008 8141h, PU4.TMDR 0008 8151h, TPU5.TMDR 0008 8161h TPU6.TMDR 0008 8181h, TPU7.TMDR 0008 8191h, TPU8.TMDR 0008 81A1h TPU9.TMDR 0008 81B1h, TPU10.TMDR 0008 81C1h, TPU11.TMDR 0008 81D1h ICSELD ICSELB...
Page 468 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) MD[3:0] Bits (Mode Select) Set the timer operating mode. BFA Bit (Buffer Operation A) Specifies whether TPUm.TGRA (m = 0, 3, 6, 9) is to normally operate, or TPUm.TGRA and TPUm.TGRC (m = 0, 3, 6, 9) are to be used together for buffer operation.
Page 469: Timer I/O Control Register (Tiorh, Tiorl, Tior)
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2.3 Timer I/O Control Register (TIORH, TIORL, TIOR) • Unit 0 (TPU0.TIORH, TPU1.TIOR, TPU2.TIOR, TPU3.TIORH, TPU4.TIOR, TPU5.TIOR) Unit 1 (TPU6.TIORH, TPU7.TIOR, TPU8.TIOR, TPU9.TIORH, TPU10.TIOR, TPU11.TIOR) Addresses: TPU0.TIORH 0008 8112h, TPU1.TIOR 0008 8122h, TPU2.TIOR 0008 8132h TPU3.TIORH 0008 8142h, TPU4.TIOR 0008 8152h, TPU5.TIOR 0008 8162h TPU6.TIORH 0008 8182h, TPU7.TIOR 0008 8192h, TPU8.TIOR 0008 81A2h TPU9.TIORH 0008 81B2h, TPU10.TIOR 0008 81C2h, TPU11.TIOR 0008 81D2h...
Page 470 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) IOA[3:0] Bits (TGRA Control) Select the function of TPUm.TGRA (m = 0 to 11). IOB[3:0] Bits (TGRB Control) Select the function of TPUm.TGRB (m = 0 to 11). IOC[3:0] Bits (TGRC Control) Select the function of TPUm.TGRC (m = 0, 3, 6, 9).
Page 471 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.15 TPU0.TIORH, TPU6.TIORH Bits IOA[3:0] Description b2 b1 TPUm.TGRA (m = 0, 6) Function TIOCAn Pin (n = 0, 6) Function Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 472 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.16 TPU1.TIOR, TPU7.TIOR Bits IOA[3:0] Description b3 b2 b0 TPUm.TGRA (m = 1, 7) Function TIOCAn Pin (n = 1, 7) Function Output compare register Output disabled Initial output is lowoutput; low output at compare match Initial output is low output;...
Page 473 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.17 TPU2.TIOR, TPU8.TIOR Bits IOA[3:0] Description b2 b1 TPUm.TGRA (m = 2, 8) Function TIOCAn Pin (n = 2, 8) Function Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 474 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.18 TPU3.TIORH, TPU9.TIORH Bits IOA[3:0] Description b3 b2 b0 TPUm.TGRA (m = 3, 9) Function TIOCAn Pin (n = 3, 9) Function Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 475 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.19 TPU4.TIOR, TPU10.TIOR Bits IOA[3:0] Description b2 b1 TPUm.TGRA (m = 4, 10) Function TIOCAn Pin (n = 4, 10) Function Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 476 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.20 TPU5.TIOR, TPU11.TIOR Bits IOA[3:0] Description b3 b2 b0 TPUm.TGRA (m = 5, 11) Function TIOCAn Pin (n = 5, 11) Function Output compare register Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 477 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.21 TPU0.TIORL, TPU6.TIORL Bits IOC[3:0] Description b3 b2 b0 TPUm.TGRC (m = 0, 6) Function TIOCCn Pin (n = 0, 6) Function Output compare register* Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 478 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.22 TPU3.TIORL, TPU9.TIORL Bits IOC[3:0] Description B2 b1 TPUm.TGRC (m = 3, 9) Function TIOCCn Pin (n = 3, 9) Function Output compare register* Output disabled Initial output is low output; low output at compare match Initial output is low output;...
Page 479: Timer Interrupt Enable Register (Tier)
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2.4 Timer Interrupt Enable Register (TIER) Addresses: TPU0.TIER 0008 8114h, TPU1.TIER 0008 8124h, TPU2.TIER 0008 8134h TPU3.TIER 0008 8144h, TPU4.TIER 0008 8154h, TPU5.TIER 0008 8164h TPU6.TIER 0008 8184h, TPU7.TIER 0008 8194h, TPU8.TIER 0008 81A4h TPU9.TIER 0008 81B4h, TPU10.TIER 0008 81C4h, TPU11.TIER 0008 81D4h —...
Page 480 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) TGIEB Bit (TGRB Interrupt Enable) Enables/disables interrupt requests (TGImB) (m = 0 to 11). TGIEC Bit (TGRC Interrupt Enable) Enables/disables interrupt requests (TGImC) (m = 0, 3, 6, 9). TGIED Bit (TGRD Interrupt Enable) Enables/disables interrupt requests (TGImD) (m = 0, 3, 6, 9).
Page 481: Timer Status Register (Tsr)
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2.5 Timer Status Register (TSR) Addresses: TPU0.TSR 0008 8115h, TPU1.TSR 0008 8125h, TPU2.TSR 0008 8135h TPU3.TSR 0008 8145h, TPU4.TSR 0008 8155h, TPU5.TSR 0008 8165h TPU6.TSR 0008 8185h, TPU7.TSR 0008 8195h, TPU8.TSR 0008 81A5h TPU9.TSR 0008 81B5h, TPU10.TSR 0008 81C5h, TPU11.TSR 0008 81D5h —...
Page 482: Timer Counter (Tcnt)
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2.6 Timer Counter (TCNT) Addresses: TPU0.TCNT 0008 8116h, TPU1.TCNT 0008 8126h, TPU2.TCNT 0008 8136h TPU3.TCNT 0008 8146h, TPU4.TCNT 0008 8156h, TPU5.TCNT 0008 8166h TPU6.TCNT 0008 8186h, TPU7.TCNT 0008 8196h, TPU8.TCNT 0008 81A6h TPU9.TCNT 0008 81B6h, TPU10.TCNT 0008 81C6h, TPU11.TCNT 0008 81D6h Value after reset: The TPU has twelve TCNT counters, one for each channel.
Page 483: Timer Start Register (Tstra, Tstrb)
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2.8 Timer Start Register (TSTRA, TSTRB) Addresses: TSTRA 0008 8100h, TSTRB 0008 8170h CST5 CST0 — — CST4 CST3 CST2 CST1 Value after reset: Symbol Bit Name Description CST0 Counter Start 0 0: TCNT count operation is stopped 1: TCNT performs count operation CST1...
Page 484: Timer Synchronous Register (Tsyra, Tsyrb)
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.2.9 Timer Synchronous Register (TSYRA, TSYRB) Addresses: TSYRA 0008 8101h, TSYRB 0008 8171h SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 — — Value after reset: Symbol Bit Name Description SYNC0 Timer Synchronization 0 0: TCNT operates independently (TCNT presetting/clearing is unrelated to other channels) SYNC1...
Page 485: Operation
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.3 Operation 15.3.1 Basic Functions Each channel has a TPUm.TCNT counter and a TPUm.TGRy register (y = A to D). TCNT is a 16-bit up-counter, and is also capable of free-running operation, periodic counting, and external event counting.
Page 486 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Free-running count operation and periodic count operation Immediately after a reset, the TPUm.TCNT counters are all set as free-running counters. When the relevant bit in TSTRA or TSTRB is set to 1, the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (changes from FFFFh to 0000h), the TPU requests an interrupt.
Page 487 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Waveform Output by Compare Match The TPU can perform low, high, or toggle output from the corresponding output pin using a compare match. Example of setting procedure for waveform output by compare match Figure 15.6 shows an example of the setting procedure for waveform output by a compare match.
Page 488 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Figure 15.8 shows an example of toggle output. In this example, TPUm.TCNT has been set as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match FFFFn...
Page 489 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Example of input capture operation Figure 15.10 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the TIOCAn pin input capture input edge, the falling edge has been selected as the TIOCBn pin input capture input edge, and counter clearing by TPUm.TGRB input capture has been set for TPUm.TCNT.
Page 490: Synchronous Operation
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.3.2 Synchronous Operation In synchronous operation, the values in multiple TPUm.TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TPUm.TCR. Synchronous operation enables TPUm.TGRy to be incremented with respect to a single time base.
Page 491 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation Figure 15.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been set for TPU0 to TPU2, TPU0.TGRB compare match has been set as the TPU0 counter clearing source, and synchronous clearing has been set for the TPU1 and TPU2 counter clearing source.
Page 492: Buffer Operation
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.3.3 Buffer Operation Buffer operation, provided for TPU0 and TPU3 (TPU6 and TPU9), enables TPUm.TGRC and TPUm.TGRD to be used as buffer registers. Buffer operation differs depending on whether TPUm.TGRy has been set as an input capture register or a compare match register.
Page 493 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) • When TPUm.TGRy is an input capture register When input capture occurs, the value in TPUm.TCNT is transferred to TGRy and the value previously held in TGRy is transferred to the buffer register. This operation is shown in figure 15.14.
Page 494 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation When TPUm.TGRy is an output compare register Figure 15.16 shows an operation example in which PWM mode 1 has been set for TPU0, and buffer operation has been set for TPU0.TGRA and TPU0.TGRC.
Page 495 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) When TPUm.TGRy is an input capture register Figure 15.17 shows an operation example in which TPUm.TGRA has been set as an input capture register, and buffer operation has been set for the TGRA register and TPUm.TGRC. Counter clearing by TGRA input capture has been set for TPUm.TCNT, and both rising and falling edges have been selected as the TIOCAn pin input capture input edge.
Page 496: Cascaded Operation
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.3.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. In the case of unit 0, this function works by counting the TPU1 (TPU4) counter clock at overflow/underflow of TPU2.TCNT (TPU5.TCNT) as set by the TPSC[2:0] bits in TPU1.TCR (TPSC[2:0] bits in TPU4.TCR).
Page 497 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation Figure 15.19 shows the operation when counting upon TPU2.TCNT overflow/underflow has been set for TPU1.TCNT, TPU1.TGRA and TPU2.TGRA have been set as input capture registers, and the rising edge of the TIOCA1 and TIOCA2 pins has been selected.
Page 498: Pwm Modes
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.3.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. low-, high-, or toggle-output can be selected as the output level in response to compare match of each TPUm.TGRy. Settings of TGRy registers can output a PWM waveform in the range of 0% to 100% duty cycle.
Page 499 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) The correspondence between PWM output pins and registers is listed in table 15.25. Table 15.25 PWM Output Registers and Output Pins Output Pin Unit Channel Register PWM Mode 1 PWM Mode 2 TPU 0 TPU0.TGRA TIOCA0...
Page 500 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure Figure 15.21 shows an example of the PWM mode setting procedure. Select the counter clock with the PWM mode TPSC[2:0] bits in TCR. At the same time, select the input clock edge with the CKEG[1:0] bits in TCR.
Page 501 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation Figure 15.22 shows an example of PWM mode 1 operation. In this example, TPUm.TGRA compare match is set as the TPUm.TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TPUm.TGRB output value.
Page 502 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Figure 15.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB changed TGRA TGRB changed TGRB TGRB changed 0000h Time 0% duty cycle TIOCA Output does not change when compare matches in cycle register and duty register occur simultaneously.
Page 503: Phase Counting Mode
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.3.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected by the settings for channels 1, 2, 4, and 5 (unit 0) and channels 7, 8, 10, and 11 (unit 1), and TPUm.TCNT is incremented/decremented accordingly. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up-/down-counter regardless of the setting of the TPSC[2:0] bits and CKEG[1:0] bits in TPUm.TCR.
Page 504 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation In phase counting mode, TPUm.TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. Phase counting mode 1 Figure 15.26 shows an example of phase counting mode 1 operation, and table 15.27 lists the TCNTn up-/down-count conditions.
Page 505 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Phase counting mode 2 Figure 15.27 shows an example of phase counting mode 2 operation, and table 15.28 lists the TPUm.TCNT up-/down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Up-count...
Page 506 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Phase counting mode 3 Figure 15.28 shows an example of phase counting mode 3 operation, and table 15.29 lists the TPUm.TCNT up-/down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Down-count...
Page 507 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Phase counting mode 4 Figure 15.29 shows an example of phase counting mode 4 operation, and table 15.30 lists the TPUm.TCNT up-/down-count conditions. TCLKA (TPU1, TPU5) TCLKC (TPU2, TPU4) TCLKB (TPU1, TPU5) TCLKD (TPU2, TPU4) TCNT value Down-count...
Page 508: Phase Counting Mode Application Example
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.3.6.1 Phase Counting Mode Application Example Figure 15.30 shows an example in which phase counting mode is set for TPU1, and TPU1 is coupled with TPU0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. TPU1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to the TCLKA and TCLKB pins.
Page 509: Interrupt Sources
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.4 Interrupt Sources There are three kinds of TPU interrupt sources: TPUm.TGRy input capture/compare match, TPUm.TCNT overflow, and TPUm.TCNT underflow. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 10, Interrupt Control Unit (ICU).
Page 510 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Table 15.31 lists the TPU interrupt sources. Table 15.31 TPU Interrupts Unit Channel Name Interrupt Source DTC Activation DMAC Activation TPU0 TGI0A TPU0.TGRA input capture/compare match Possible Possible TGI0B TPU0.TGRB input capture/compare match Possible Not possible TGI0C...
Page 511 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) TPU9 TGI9A TPU9.TGRA input capture/compare match Possible Possible TGI9B TPU9.TGRB input capture/compare match Possible Not possible TGI9C TPU9.TGRC input capture/compare match Possible Not possible TGI9D TPU9.TGRD input capture/compare match Possible Not possible TCI9V TPU9.TCNT overflow Not poss ble...
Page 512: Dtc Activation
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.5 DTC Activation The DTC can be activated by the TPUm.TGRy input capture/compare match interrupt of each channel. For details, see section 13, Data Transfer Controller (DTC). A total of 32 input capture/compare match interrupts can be used as DTC activation sources, four each for TPU0 and TPU3 (TPU6 and TPU9), and two each for TPU1, TPU2, TPU4, and TPU5 (TPU7, TPU8, TPU10, and TPU11).
Page 513: Operation Timing
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.8 Operation Timing 15.8.1 Input/Output Timing TPUm.TCNT Count Timing Figure 15.31 shows TPUm.TCNT count timing in internal clock operation, and figure 15.32 shows TCNT count timing in external clock operation. PCLK Falling edge Internal clock Rising edge Falling edge...
Page 514 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing A compare match signal is generated in the final state in which TPUm.TCNT and TPUm.TGRy match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TPUm.TIORH, TPUm.TIORL, or TPUm.TIOR is output to the output compare output pin TIOCyn (y = A to D, n = 0 to 11).
Page 515 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture Figure 15.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 15.36 shows the timing when counter clearing by input capture occurrence is specified. PCLK Compare match signal...
Page 516 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing Figures 15.37 and 15.38 show the timings in buffer operation. PCLK TCNT N + 1 Compare match signal TGRA, TGRB TGRC, TGRD Figure 15.37 Buffer Operation Timing (Compare Match) PCLK Input capture signal TCNT...
Page 517: Interrupt Signal Timing
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.8.2 Interrupt Signal Timing Interrupt Flag Setting to 1 in Case of Compare Match Figure 15.39 shows the timing for setting the interrupt flag by compare match occurrence. PCLK TCNT input clock N + 1 TCNT TGRy...
Page 518 RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) TCImV/TCImU Interrupt Flag Setting to 1 Figure 15.41 shows the timing for generating the TCImV interrupt request signal by overflow occurrence. Figure 15.42 shows the timing for generating the TCImU interrupt request signal by underflow occurrence. PCLK TCNT input clock TCNT (overflow)
Page 519: Usage Notes
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.9 Usage Notes 15.9.1 Module Stop Function Setting Operation of the TPU can be disabled or enabled using the module stop control register. The TPU does not operate with the initial setting. Register access is enabled by clearing module stop state. For details, see section 8, Low Power Consumption.
Page 520: Caution On Cycle Setting
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.9.3 Caution on Cycle Setting When counter clearing by compare match is set, TPUm.TCNT is cleared in the final state in which it matches the TPUm.TGRy value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: PCLK (N + 1)
Page 521: Conflict Between Tpum.tgry Write And Compare Match
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.9.6 Conflict between TPUm.TGRy Write and Compare Match If a compare match occurs in a TGRy write cycle, the TGRy write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 15.46 shows the timing in this case.
Page 522: Conflict Between Tpum.tgry Read And Input Capture
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.9.8 Conflict between TPUm.TGRy Read and Input Capture If the input capture signal is generated in a TGRy read cycle, the data that is read will be the data before input capture transfer.
Page 523: Conflict Between Buffer Register Write And Input Capture
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.9.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 15.50 shows the timing in this case. Buffer register write by CPU PCLK Input capture signal...
Page 524: Conflict Between Tpum.tcnt Write And Overflow/Underflow
RX610 Group 15. 16-Bit Timer Pulse Unit (TPU) 15.9.12 Conflict between TPUm.TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in a TCNT write cycle, the TCNT write takes precedence. Figure 15.52 shows the operation timing when there is conflict between TCNT write and overflow. TCNT write by CPU PCLK TCNT write data...
Page 525: Overview
RX610 Group 16. Programmable Pulse Generator (PPG) Programmable Pulse Generator (PPG) The programmable pulse generator (PPG) generates pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The RX610 Group has two PPG units, each of which controls up to 16 pulse output pins. The pulse outputs from the PPGs are divided into 4-bit groups that can operate all simultaneously and independently.
Page 526 RX610 Group 16. Programmable Pulse Generator (PPG) Compare match signals NDERH NDERL Control logic PO15 PO14 Pulse output PO13 pins, group 3 PO12 PODRH NDRH PO11 Pulse output PO10 pins, group 2 Pulse output pins, group 1 NDRL PODRL Pulse output pins, group 0 [Legend] PMR:...
Page 527 RX610 Group 16. Programmable Pulse Generator (PPG) Compare match signals NDERL NDERH Control logic PTRSLR PO31 Pulse output PO30 PO29 pins, group 7 PO28 NDRH PODRH PO27 Pulse output PO26 PO25 pins, group 6 PO24 PO23 Pulse output PO22 pins, group 5 PO21 PO20 NDRL...
Page 528 RX610 Group 16. Programmable Pulse Generator (PPG) Table 16.3 lists the pin configuration of the PPG. Table 16.3 Pin Configuration of PPG Unit Pin Name Function PPG0 Output Group 0 pulse output Output Output Output Output Group 1 pulse output Output Output Output...
Page 529: Register Descriptions
RX610 Group 16. Programmable Pulse Generator (PPG) 16.2 Register Descriptions Table 16.4 lists the registers of the PPG. Table 16.4 Registers of PPG Unit Register Name Symbol Value after Reset Address Access Size PPG0 PPG output control register 0008 81E6h PPG output mode register 0008 81E7h Next data enable register H...
Page 530: Ppg Trigger Select Register (Ptrslr)
RX610 Group 16. Programmable Pulse Generator (PPG) 16.2.1 PPG Trigger Select Register (PTRSLR) Address: 0008 81F0h — — — — — — — PTRSL Value after reset: • PPG1.PTRSLR Symbol Bit Name Description PTRSL PPG Trigger Select 0: Selects the set of TPU0 toTPU3 as the trigger channels for PPG1.
Page 531: Next Data Enable Registers H And L (Nderh, Nderl)
RX610 Group 16. Programmable Pulse Generator (PPG) 16.2.2 Next Data Enable Registers H and L (NDERH, NDERL) Address: 0008 81E8h PPG0.NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Value after reset: Address: 0008 81E9h PPG0.NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1...
Page 532 RX610 Group 16. Programmable Pulse Generator (PPG) • PPG0.NDERL Symbol Bit Name Description NDER0 Next Data Transfer Enable 0: Data transfer is disabled. 1: Data transfer is enabled. NDER1 Next Data Transfer Enable NDER2 Next Data Transfer Enable NDER3 Next Data Transfer Enable NDER4 Next Data Transfer Enable NDER5...
Page 533 RX610 Group 16. Programmable Pulse Generator (PPG) Address: 0008 81F8h PPG1.NDERH NDER31 NDER30 NDER29 NDER28 NDER27 NDER26 NDER25 NDER24 Value after reset: Address: 0008 81F9h PPG1.NDERL NDER23 NDER22 NDER21 NDER20 NDER19 NDER18 NDER17 NDER16 Value after reset: • PPG1.NDERH Symbol Bit Name Description NDER24...
Page 534 RX610 Group 16. Programmable Pulse Generator (PPG) • PPG1.NDERL Symbol Bit Name Description NDER16 Next Data Transfer Enable 0: Data transfer is disabled. 1: Data transfer is enabled. NDER17 Next Data Transfer Enable NDER18 Next Data Transfer Enable NDER19 Next Data Transfer Enable NDER20 Next Data Transfer Enable NDER21...
Page 535: Output Data Registers H And L (Podrh, Podrl)
RX610 Group 16. Programmable Pulse Generator (PPG) 16.2.3 Output Data Registers H and L (PODRH, PODRL) Address: 0008 81EAh PPG0.PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Value after reset: Address: 0008 81EBh PPG0.PODRL POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0...
Page 536 RX610 Group 16. Programmable Pulse Generator (PPG) Address: 0008 81FAh PPG1.PODRH POD31 POD30 POD29 POD28 POD27 POD26 POD25 POD24 Value after reset: Address: 0008 81FBh PPG1.PODRL POD23 POD22 POD21 POD20 POD19 POD18 POD17 POD16 Value after reset: • PPG1.PODRH Symbol Bit Name Description POD24...
Page 537: Next Data Registers H And L (Ndrh, Ndrl)
RX610 Group 16. Programmable Pulse Generator (PPG) 16.2.4 Next Data Registers H and L (NDRH, NDRL) Addresses: 0008 81ECh, 0008 81EEh PPG0.NDRH NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Value after reset: Addresses: 0008 81EDh, 0008 81EFh PPG0.NDRL NDR7 NDR6 NDR5 NDR4...
Page 538 RX610 Group 16. Programmable Pulse Generator (PPG) (Pulse output group 2: 0008 81EEh) Symbol Bit Name Description NDR8 Next Data Register The output trigger specified by PPG0.PCR transfers the values in this register to the corresponding bits in PPG0.PODRH. NDR9 Next Data Register NDR10 Next Data Register...
Page 539 RX610 Group 16. Programmable Pulse Generator (PPG) (Pulse output group 0: 0008 81EFh) Symbol Bit Name Description NDR0 Next Data Register The output trigger specified by PPG0.PCR transfers the values in this register to the corresponding bits in PPG0.PODRL. NDR1 Next Data Register NDR2 Next Data Register...
Page 540 RX610 Group 16. Programmable Pulse Generator (PPG) (2) When pulse output groups 6 and 7 have different output triggers If pulse output groups 6 and 7 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses.
Page 541 RX610 Group 16. Programmable Pulse Generator (PPG) (2) When pulse output groups 4 and 5 have different output triggers If pulse output groups 4 and 5 have different output triggers, upper 4 bits and lower 4 bits are mapped to the different addresses.
Page 542: Ppg Output Control Register (Pcr)
RX610 Group 16. Programmable Pulse Generator (PPG) 16.2.5 PPG Output Control Register (PCR) Addresses: PPG0.PCR 0008 81E6h, PPG1.PCR 0008 81F6h G3CMS[1:0] G2CMS[1:0] G1CMS[1:0] G0CMS[1:0] Value after reset: • PPG0.PCR Symbol Bit Name Description b1, b0 G0CMS[1:0] Group 0 Compare Match Select b1 b0 0 0: Compare match in TPU0 0 1: Compare match in TPU1...
Page 543 RX610 Group 16. Programmable Pulse Generator (PPG) Symbol Bit Name Description b3, b2 G1CMS[1:0] Group 5 Compare Match Select • When the PTRSL bit in PPG1.PTRSLR is set to 0. b3 b2 0 0: Compare match in TPU0 0 1: Compare match in TPU1 1 0: Compare match in TPU2 1 1: Compare match in TPU3 •...
Page 544: Ppg Output Mode Register (Pmr)
RX610 Group 16. Programmable Pulse Generator (PPG) 16.2.6 PPG Output Mode Register (PMR) Addresses: PPG0.PMR 0008 81E7h, PPG1.PMR 0008 81F7h G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Value after reset: • PPG0.PMR Symbol Bit Name Description G0NOV Group 0 Non-Overlap 0: Normal operation (Output values updated on compare match A in the selected TPUm)
Page 545 RX610 Group 16. Programmable Pulse Generator (PPG) • PPG1.PMR Symbol Bit Name Description G0NOV Group 4 Non-Overlap 0: Normal operation (Output values updated on compare match A in the selected TPUm) 1: Non-overlapping operation (Output values updated on compare match A or B in the selected TPUm) (m = 0 to 3, 6 to 9) G1NOV...
Page 546 RX610 Group 16. Programmable Pulse Generator (PPG) GjNOV Bits (Group k Non-Overlap) (j = 0 to 3, k = 0 to 7) Each bit selects normal operation or non-overlapping operation for pulse output group j. GjINV Bits (Group k Invert) (j = 0 to 3, k = 0 to 7) Each bit selects direct output or inverted output for pulse output group k.
Page 547: Operation
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3 Operation Figure 16.4 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in PPGm.NDERH and PPGm.NDERL (m = 0, 1) are set to 1 (data transfer is enabled). An initial output value is determined by the initial settings in the corresponding PPGm.PODRH and PPGm.PODRL.
Page 548: Output Timing
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3.1 Output Timing When the selected compare match event occurs while pulse output is enabled, the values in PPGm.NDRH and PPGm.NDRL (m = 0, 1) are transferred to PPGm.PODRH and PPGm.PODRL, respectively, and then output on the corresponding pins.
Page 549: Sample Setup Procedure For Normal Pulse Output
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3.2 Sample Setup Procedure for Normal Pulse Output Figures 16.6 and 16.7 show sample procedures for setting normal pulse output. PPG0 Setting Normal PPG output Set TIOR of the TPU (unit 0) to make TGRA an output Select TGR functions compare register (output disabled).
Page 550 RX610 Group 16. Programmable Pulse Generator (PPG) PPG1 Setting Normal PPG output In the case of unit 0, set TIOR of the TPU to make Select TGR functions TGRA an output compare register (output disabled). In the case of unit 1, set TIOR of the TPU to make Set TGRA values TGRA an output compare register (toggle output).
Page 551: Example Of Normal Pulse Output (Example Of Five-Phase Pulse Output)
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3.3 Example of Normal Pulse Output (Example of Five-Phase Pulse Output) Figure 16.8 shows an example in which pulse output from the PPG0 is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA 0000h...
Page 552: Non-Overlapping Pulse Output
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3.4 Non-Overlapping Pulse Output During non-overlapping operation, data transfer from PPGm.NDRH and PPGm.NDRL (m = 0, 1) to PPGm.PODRH and PPGm. PODRL is performed as follows. • On compare match A, the values in PPGm.NDRH and PPGm.NDRL are always transferred to PPGm.PODRH and PPGm.
Page 553 RX610 Group 16. Programmable Pulse Generator (PPG) Compare match A Compare match B Write to NDR Write to NDR PODR Low output Low /High output Low output Low /High output Write to NDR here Write to NDR here Do not write to Do not write to NDR here NDR here...
Page 554: Sample Setup Procedure For Non-Overlapping Pulse Output
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3.5 Sample Setup Procedure for Non-Overlapping Pulse Output Figures 16.11 and 16.12 show sample procedures for setting up non-overlapping pulse outputs. PPG0 Setting Non-overlapping pulse output Select TGR functions Set TIOR of the TPU (unit 0) to make TGRA and TGRB output compare registers (output disabled).
Page 555 RX610 Group 16. Programmable Pulse Generator (PPG) PPG1 Setting Non-overlapping pulse output Select TGR functions In the case of unit 0, set TIOR of the TPU to make TGRA and TGRB output compare registers (output Set TGR values disabled). TPU (units 0 and 1) setup In the case of unit 1, set TIOR of the TPU to make TGRA and TGRB output compare registers (toggle Set counting operations...
Page 556: Example Of Non-Overlapping Pulse Output (Example Of Four-Phase Complementary Non-Overlapping Output)
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3.6 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 16.13 shows an example in which pulse output from the PPG0 is used for four-phase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA...
Page 557 RX610 Group 16. Programmable Pulse Generator (PPG) Set output compare registers of the TPU, i.e. TPUm.TGRA and TPUm.TGRB (m = 0 to 3) so that the corresponding compare match signals are the output triggers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B.
Page 558: Inverted Pulse Output
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3.7 Inverted Pulse Output When the G3INV, G2INV, G1INV, and G0INV bits in PPG0.PMR are cleared to 0, the values that are the inverse of the respective values in PPG0.PODRH and PPG0.PODRL can be output. Figure 16.14 shows the outputs when the G3INV and G2INV bits are cleared to 0 in addition to the settings in figure 16.13.
Page 559: Pulse Output Triggered By Input Capture
RX610 Group 16. Programmable Pulse Generator (PPG) 16.3.8 Pulse Output Triggered by Input Capture Pulse output from the PPG0 can be triggered by the TPU (unit 0) input capture as well as by compare match. When a TPUm.TGRA (m = 0 to 3) functions as an input capture register in the TPU (unit 0) channel selected by PPG0.PCR, pulse output is triggered by the input capture signal.
Page 560: Usage Note
RX610 Group 16. Programmable Pulse Generator (PPG) 16.4 Usage Note 16.4.1 Module Stop Function Setting Operation of the PPG can be disabled or enabled by the module stop control register. The initial setting is for operation of the PPG to be halted. Register access is enabled by clearing module stop state. For details, see section 8, Low Power Consumption.
Page 561: Overview
RX610 Group 17. 8-Bit Timer (TMR) 8-Bit Timer (TMR) The RX610 Group has two units (unit 0, unit 1) of an on-chip 8-bit timer (TMR) module that comprise two 8-bit counter channels, totaling four channels. The 8-bit timer module can be used to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers.
Page 562 RX610 Group 17. 8-Bit Timer (TMR) Internal clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Counter clock 1 Counter clock 0 TMCI0 Clock select TMCI1 TCORA TCORA Compare match A1 Compare match A0 Comparator A0 Comparator A1 To SCI5 Overflow 1 Overflow 0 TCNT TCNT...
Page 563 RX610 Group 17. 8-Bit Timer (TMR) Internal clock PCLK PCLK/2 PCLK/8 PCLK/32 PCLK/64 PCLK/1024 PCLK/8192 Counter clock 3 Counter clock 2 TMCI2 Clock select TMCI3 TCORA TCORA Compare match A3 Comparator A2 Comparator A3 Compare match A2 To SCI6 Overflow 3 TCNT TCNT TMO2...
Page 564 RX610 Group 17. 8-Bit Timer (TMR) Table 17.2 lists the input/output pins of the TMR. Table 17.2 Pin Configuration of TMR Unit Channel Pin Name Description TMR0 TMO0 Output Outputs compare match TMCI0 Input Inputs external clock for counter TMRI0 Input Inputs external reset to counter TMR1...
Page 565: Register Descriptions
RX610 Group 17. 8-Bit Timer (TMR) 17.2 Register Descriptions Table 17.3 shows the registers of the TMR. Table 17.3 Registers of TMR Value after Access Unit Channel Register Name Symbol Reset Address* Size TMR0 Timer counter TCNT 0008 8208h 8 or 16 Time constant register A TCORA 0008 8204h...
Page 566: Timer Counter (Tcnt)
RX610 Group 17. 8-Bit Timer (TMR) 17.2.1 Timer Counter (TCNT) Addresses: TMR0.TCNT 0008 8208h, TMR1.TCNT 0008 8209h TMR2.TCNT 0008 8218h, TMR3.TCNT 0008 8219h TMR0.TCNT (TMR2.TCNT) TMR1.TCNT (TMR3.TCNT) Value after reset: TCNT is an 8-bit readable/writable up-counter. TMR0.TCNT and TMR1.TCNT (TMR2.TCNT and TMR3.TCNT) comprise a single 16-bit counter so they can be accessed together by a word transfer instruction.
Page 567: Time Constant Register B (Tcorb)
RX610 Group 17. 8-Bit Timer (TMR) 17.2.3 Time Constant Register B (TCORB) Addresses: TMR0.TCORB 0008 8206h, TMR1.TCORB 0008 8207h TMR2.TCORB 0008 8216h, TMR3.TCORB 0008 8217h TMR0.TCORB (TMR2.TCORB) TMR1.TCORB (TMR3.TCORB) Value after reset: TCORB is an 8-bit readable/writable register. TMR0.TCORB and TMR1.TCORB (TMR2.TCORB and TMR3.TCORB) comprise a single 16-bit register so they can be accessed together by a word transfer instruction.
Page 568: Timer Control Register (Tcr)
RX610 Group 17. 8-Bit Timer (TMR) 17.2.4 Timer Control Register (TCR) Addresses: TMR0.TCR 0008 8200h, TMR1.TCR 0008 8201h TMR2.TCR 0008 8210h, TMR3.TCR 0008 8211h CCLR[1:0] CMIEB CMIEA OVIE Value after reset: Symbol Bit Name Description  b2 to b0 Reserved These bits are always read as 0.
Page 569: Timer Counter Control Register (Tccr)
RX610 Group 17. 8-Bit Timer (TMR) 17.2.5 Timer Counter Control Register (TCCR) Addresses: TMR0.TCCR 0008 820Ah, TMR1.TCCR 0008 820Bh TMR2.TCCR 0008 821Ah, TMR3.TCCR 0008 821Bh TMRIS CSS[1:0] CKS[2:0] Value after reset: Symbol Bit Name Description b2 to b0 CKS[2:0] Clock Select* See table 17.5.
Page 570 RX610 Group 17. 8-Bit Timer (TMR) Table 17.5 Clock Input to TCNT and Count Condition TCCR Register CSS[1:0] CKS[2:0] Channel Description  TMR0 Clock input prohibited (TMR2) Uses external clock. Counts at rising edge* Uses external clock. Counts at falling edge* Uses external clock.
Page 571: Timer Control/Status Register (Tcsr)
RX610 Group 17. 8-Bit Timer (TMR) 17.2.6 Timer Control/Status Register (TCSR) Addresses: TMR0.TCSR 0008 8202h, TMR2.TCSR 0008 8212h — — — ADTE OSB[1:0] OSA[1:0] Value after reset: Addresses: TMR1.TCSR 0008 8203h, TMR3.TCSR 0008 8213h — — — — OSB[1:0] OSA[1:0] Value after reset: [Legend] x: Undefined •...
Page 572 RX610 Group 17. 8-Bit Timer (TMR) • TMR1.TCSR, TMR3.TCSR Symbol Bit Name Description b1, b0 OSA[1:0] Output Select A* b1 b0 0 0: No change when compare match A occurs 0 1: Low is output when compare match A occurs 1 0: High is output when compare match A occurs 1 1: Output is inverted when compare match A occurs (toggle output)
Page 573: Operation
RX610 Group 17. 8-Bit Timer (TMR) 17.3 Operation 17.3.1 Pulse Output Figure 17.3 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. 1. Set the TCR.CCLR[1:0] bits to 01b (cleared by compare match A) so that TCNT is cleared at a compare match of TCORA.
Page 574: Reset Input
RX610 Group 17. 8-Bit Timer (TMR) 17.3.2 Reset Input Figure 17.4 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRIn input. 1. Set the TCR.CCLR[1:0] bits to 11b (cleared by external reset input) and set the TMRIS bit in TCCR to high (cleared when the external reset is high) so that TCNT is cleared at the high level input of the TMRIn signal.
Page 575: Operation Timing
RX610 Group 17. 8-Bit Timer (TMR) 17.4 Operation Timing 17.4.1 TCNT Count Timing Figure 17.5 shows the count timing of TCNT for internal clock input. Figure 17.6 shows the count timing of TCNT for external clock input. Note that the external clock pulse width must be at least 1.5 states for increment at a single edge, and at least 2.5 states for increment at both edges.
Page 576: Timing Of Interrupt Flag Setting To 1 At Compare Match
RX610 Group 17. 8-Bit Timer (TMR) 17.4.2 Timing of Interrupt Flag Setting to 1 at Compare Match The interrupt flag is set to 1 by a compare match signal generated when values of TCORA and TCORB and that of TCNT match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Page 577: Timing Of Timer Output At Compare Match
RX610 Group 17. 8-Bit Timer (TMR) 17.4.3 Timing of Timer Output at Compare Match When a compare match signal is generated, the timer output changes as specified by the TCSR.OSA[1:0] and OSB[1:0] bits. Figure 17.8 shows the timing when the timer output is toggled by the compare match A signal. PCLK Compare match A signal Timer output pin...
Page 578: Timing Of The External Reset For Tcnt
RX610 Group 17. 8-Bit Timer (TMR) 17.4.5 Timing of the External Reset for TCNT TCNT is cleared at the rising edge or high level of an external reset input, depending on the settings of the TCR.CCLR[1:0] bits. At least 2 states are required from an external reset input to clearing of TCNT. Figures 17.10 and 17.11 show the timing of this operation.
Page 579: Timing Of Overflow Interrupt Flag Setting To 1
RX610 Group 17. 8-Bit Timer (TMR) 17.4.6 Timing of Overflow Interrupt Flag Setting to 1 The interrupt flag is set to 1 by an overflow signal outputted when TCNT overflows (changes from FFh to 00h). Figure 17.12 shows the timing of this operation. For details on the corresponding interrupt vector number, see section 10, Interrupt Control Unit (ICU) and table 17.6, TMR Interrupt Sources.
Page 580: Operation With Cascaded Connection
RX610 Group 17. 8-Bit Timer (TMR) 17.5 Operation with Cascaded Connection If the CSS[1:0] bits in either TMR0.TCCR or TMR1.TCCR are set to 11b, the TMR of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit count mode) or compare matches of TMR0 could be counted by TMR1 (compare match count mode).
Page 581: Interrupt Sources
RX610 Group 17. 8-Bit Timer (TMR) 17.6 Interrupt Sources 17.6.1 Interrupt Sources and DTC Activation There are three interrupt sources for TMRn: CMIAm, CMIBm, and OVIm. Their interrupt sources and priorities are listed in table 17.6. It is also possible to activate the DTC by means of CMIAm and CMIBm interrupts. The DMAC cannot be activated by the interrupt sources for TMRn.
Page 582: Usage Notes
RX610 Group 17. 8-Bit Timer (TMR) 17.7 Usage Notes 17.7.1 Module Stop State Setting Operation of the TMR can be disabled or enabled by using the module-stop control registers. The initial setting is for halting of TMR operation. Register access becomes possible after release from the module-stop state. For details, see section 8, Power-Down Modes.
Page 583: Conflict Between Tcnt Write And Increment
RX610 Group 17. 8-Bit Timer (TMR) 17.7.4 Conflict between TCNT Write and Increment Even if a counting-up signal is generated concurrently with CPU write to TCNT, the counting-up is not performed and the write takes priority as shown in figure 17.14. TCNT write by CPU PCLK TCNT...
Page 584: Conflict Between Tcora Or Tcorb Write And Compare Match
RX610 Group 17. 8-Bit Timer (TMR) 17.7.5 Conflict between TCORA or TCORB Write and Compare Match Even if a compare match signal is generated simultaneously with CPU write to TCORA or TCORB, the write takes priority and the compare match signal is not set as shown in figure 17.15. Write to TCORy by CPU PCLK TCNT...
Page 585: Switching Of Internal Clocks And Tcnt Operation
RX610 Group 17. 8-Bit Timer (TMR) 17.7.7 Switching of Internal Clocks and TCNT Operation TCNT may be incremented erroneously depending on when the internal clock is switched. Table 17.8 shows the relationship between the timing at which the internal clock is switched (by writing to the TCCR.CKS[2:0] bits) and the operation of TCNT.
Page 586: Clock Source Setting With Cascaded Connection
RX610 Group 17. 8-Bit Timer (TMR) Timing to Change the TCCR.CKS[2:0] Bits TCNT Clock Operation Clock before Switching from high to low* switching Clock after switching TCNT input clock TCNT TCCR.CKS[2:0] bits changed Clock before Switching from high to high switching Clock after switching...
Page 587: Overview
RX610 Group 18. Compare Match Timer (CMT) Compare Match Timer (CMT) The RX610 Group has two on-chip compare match timer (CMT) units (unit 0 and unit 1) each consisting of a two-channel 16-bit timer (i.e., a total of four channels). The CMT has a 16-bit counter, and can generate interrupts at set intervals.
Page 588: Register Descriptions
RX610 Group 18. Compare Match Timer (CMT) 18.2 Register Descriptions Table 18.2 lists the registers of the CMT. Table 18.2 List of CMT Registers Value after Unit Channel Register Name Symbol Reset Address Access Size Unit 0 Common Compare match timer start register 0 CMSTR0 0000h 0008 8000h...
Page 589: Compare Match Timer Start Register 0 (Cmstr0)
RX610 Group 18. Compare Match Timer (CMT) 18.2.1 Compare Match Timer Start Register 0 (CMSTR0) Address: 0008 8000h — — — — — — — — Value after reset: — — — — — — STR1 STR0 Value after reset: Symbol Bit Name Description...
Page 590: Compare Match Timer Start Register 1 (Cmstr1)
RX610 Group 18. Compare Match Timer (CMT) 18.2.2 Compare Match Timer Start Register 1 (CMSTR1) Address: 0008 8010h — — — — — — — — Value after reset: — — — — — — STR3 STR2 Value after reset: Symbol Bit Name Description...
Page 591: Compare Match Timer Control Register (Cmcr)
RX610 Group 18. Compare Match Timer (CMT) 18.2.3 Compare Match Timer Control Register (CMCR) Addresses: CMT0.CMCR 0008 8002h, CMT1.CMCR 0008 8008h, CMT2.CMCR 0008 8012h, CMT3.CMCR 0008 8018h — — — — — — — — Value after reset: CMIE CKS[1:0] —...
Page 592: Compare Match Counter (Cmcnt)
RX610 Group 18. Compare Match Timer (CMT) 18.2.4 Compare Match Counter (CMCNT) Addresses: CMT0.CMCNT 0008 8004h, CMT1.CMCNT 0008 800Ah, CMT2.CMCNT 0008 8014h, CMT3.CMCNT 0008 801Ah Value after reset: CMCNT is a readable/writable up-counter to generate interrupt requests. When an internal clock is selected by bits CKS[1:0] in CMCR and the STRj (j = 0 to 3) bit in CMSTRy (y = 0 or 1) is set to 1, CMCNT starts counting up using the selected clock.
Page 593: Operation
RX610 Group 18. Compare Match Timer (CMT) 18.3 Operation 18.3.1 Periodic Count Operation When an internal clock is selected by bits CKS[1:0] in CMCR and the STRj (j = 0 to 3) bit in CMSTRy (y = 0 or 1) is set to 1, CMCNT starts counting up using the selected clock.
Page 594: Interrupts
RX610 Group 18. Compare Match Timer (CMT) 18.4 Interrupts 18.4.1 Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has a compare match interrupt (CMIm) (m = 0 to 3). When a compare match interrupt occurs, the corresponding interrupt request is output. When the interrupt is used to activate a CPU interrupt, the priority of channels can be changed by the interrupt control unit settings.
Page 595: Usage Notes
RX610 Group 18. Compare Match Timer (CMT) 18.5 Usage Notes 18.5.1 Setting the Module Stop Function The CMT can be enabled or disabled using the module stop control register. The CMT is disabled by default. The registers can be accessed by canceling the module stop state. For details, see section 8, Low Power Consumption. 18.5.2 Conflict between Write and Compare-Match Processes of CMCNT When the compare match signal is generated while writing to CMCNT, clearing CMCNT has priority over writing to it.
Page 596: Notes On Rewriting Compare Match Timer Control Register (Cmcr)
RX610 Group 18. Compare Match Timer (CMT) 18.5.4 Notes on Rewriting Compare Match Timer Control Register (CMCR) When rewriting to the CMCR competes with generation of the compare match, writing to the CMCR is ignored. Therefore, it is necessary to check if data is written correctly by reading the CMCR after writing to the CMCR. If the data is not written correctly, once again the writing should be carried out to the CMCR.
Page 597: Overview
RX610 Group 19. Watchdog Timer (WDT) Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF#) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal.
Page 598 RX610 Group 19. Watchdog Timer (WDT) Overflow PCLK/4 Interrupt WOVI PCLK/64 control (Interrupt request signal) PCLK/128 PCLK/512 Clock Clock PCLK/2048 selection PCLK/8192 WDTOVF# PCLK/32768 (Overflow signal) PCLK/131072 Reset control Internal reset signal* Internal clocks RSTCSR TCNT TCSR Internal main bus Peripheral bus interface Peripheral bus...
Page 599: Register Descriptions
RX610 Group 19. Watchdog Timer (WDT) 19.2 Register Descriptions Table 19.3 lists the registers of the WDT. Table 19.3 WDT Registers Register Name Symbol Value after Reset Address Access Size Timer control/status register TCSR 0008 8028h Timer counter TCNT 0008 8029h Reset control/status register RSTCSR 0008 802Bh...
Page 600: Timer Control/Status Register (Tcsr)
RX610 Group 19. Watchdog Timer (WDT) 19.2.2 Timer Control/Status Register (TCSR) Address: 0008 8028h CKS[2:0] — — — Value after reset: [Legend] x: Undefined Symbol Bit Name Description b2 to b0 CKS[2:0] Clock Select b2 b0 0 0 0: PCLK/4 (cycle: 20.4 µs) 0 0 1: PCLK/64 (cycle: 326.4 µs) 0 1 0: PCLK/128 (cycle: 652.8 µs) 0 1 1: PCLK/512 (cycle: 2.6 ms)
Page 601: Reset Control/Status Register (Rstcsr)
RX610 Group 19. Watchdog Timer (WDT) 19.2.3 Reset Control/Status Register (RSTCSR) Address: 0008 802Bh — — — — — — WOVF RSTE Value after reset: Symbol Bit Name Description  b4 to b0 Reserved These bits are always read as 1. The write value should always be 1.
Page 602: Write Window A Register (Wina)
RX610 Group 19. Watchdog Timer (WDT) 19.2.4 Write Window A Register (WINA) Address: 0008 8028h — — — — — — — — — — — — — — — — Value after reset: WINA is a write-only register for writing to TCNT and TCSR. The writing method varies between TCNT and TCSR.
Page 603: Operation
RX610 Group 19. Watchdog Timer (WDT) 19.3 Operation 19.3.1 Watchdog Timer Mode To use the WDT in watchdog timer mode, set both the TMS bit and TME bit in TCSR to 1. During watchdog timer operation, if TCNT overflows without being rewritten because of a system crash or another error, the WDTOVF# signal is output.
Page 604: Interval Timer Mode
RX610 Group 19. Watchdog Timer (WDT) 19.3.2 Interval Timer Mode To use the WDT as an interval timer, set the TMS bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time TCNT overflows. Therefore, an interrupt can be generated at intervals.
Page 605: Usage Notes
RX610 Group 19. Watchdog Timer (WDT) 19.5 Usage Notes 19.5.1 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR differ from other registers in being more difficult to write to. (1) Writing to TCNT Counter, TCSR Register, and RSTCSR Register When writing to TCNT and TCSR, be sure to use a word transfer instruction to the write window A register (WINA) (00088028h).
Page 606: Conflict Between Timer Counter (Tcnt) Write And Increment
RX610 Group 19. Watchdog Timer (WDT) (2) Reading from TCNT Counter, TCSR Register, and RSTCSR Register These counter and registers can be read from in the same way as other registers. TCSR is assigned to address 00088028h, TCNT to address 00088029h, and RSTCSR to address 0008802Ah. For reading, use 8-bit access.
Page 607: Switching Between Watchdog Timer Mode And Interval Timer Mode
RX610 Group 19. Watchdog Timer (WDT) 19.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode If the timer mode is switched from watchdog timer mode to interval timer mode while the watchdog timer is operating, errors could occur in the operation. The watchdog timer must be stopped (by clearing the TME bit in TCSR to 0) before switching the timer mode.
Page 608: Overview
RX610 Group 20. Serial Communications Interface (SCI) Serial Communications Interface (SCI) The RX610 Group has seven independent serial communications interface (SCI) units. The SCI can handle both asynchronous and clock synchronous serial communications. Asynchronous serial data communications can be carried out with standard asynchronous communications chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA).
Page 609 RX610 Group 20. Serial Communications Interface (SCI) Table 20.2 Function List of SCI Channels Item SCI0 to SCI4 SCI5 and SCI6 Asynchronous mode Possible Possible Clock synchronous mode Possible Possible Smart card interface mode Possible Possible TMR clock input Not possible Possible Module data bus SCMR...
Page 610 RX610 Group 20. Serial Communications Interface (SCI) Module data bus SCMR PCLK Baud rate RxDn PCLK/4 generator SEMR PCLK/16 Transmission PCLK/64 and reception control TxDn Parity error occurrence Clock Parity check External clock SCKn TMO0, TMO2 TMO1, TMO3 [Legend] RSR: Receive shift register SCR: Serial control register...
Page 611 RX610 Group 20. Serial Communications Interface (SCI) Table 20.3 lists the pin configuration of the SCI. Table 20.3 Pin Configuration of SCI Channel Pin Name Function SCI0 SCK0 SCI0 clock input/output RxD0 Input SCI0 receive data input TxD0 Output SCI0 transmit data output SCI1 SCK1 SCI1 clock input/output...
Page 612: Register Descriptions
RX610 Group 20. Serial Communications Interface (SCI) 20.2 Register Descriptions Table 20.4 lists the registers of the SCI. Table 20.4 Registers of SCI Channel Register Name Symbol Value after Reset Address Access Size SCI0 Serial mode register 0008 8240h Bit rate register 0008 8241h Serial control register 0008 8242h...
Page 613 RX610 Group 20. Serial Communications Interface (SCI) Bit rate register 0008 8269h Serial control register 0008 826Ah Transmit data register 0008 826Bh Serial status register 0008 826Ch Receive data register 0008 826Dh Smart card mode register SCMR 0008 826Eh Serial extended mode register SEMR 0008 826Fh SCI6...
Page 614: Receive Shift Register (Rsr)
RX610 Group 20. Serial Communications Interface (SCI) 20.2.1 Receive Shift Register (RSR) RSR is a shift register which is used to receive serial data input from the RxDn pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU.
Page 615: Transmit Shift Register (Tsr)
RX610 Group 20. Serial Communications Interface (SCI) 20.2.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, and then sends the data to the TxDn pin.
Page 616 RX610 Group 20. Serial Communications Interface (SCI) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. CKS[1:0] Bits (Clock Select) These bits select the clock source for the baud rate generator. For the relation between the settings of these bits and the baud rate, see section 20.2.9, Bit Rate Register (BRR).
Page 617 RX610 Group 20. Serial Communications Interface (SCI) (2) Smart Card Interface Mode (SMIF in SCMR = 1) Addresses: SCI0.SMR 0008 8240h, SCI1.SMR 0008 8248h, SCI2.SMR 0008 8250h, SCI3.SMR 0008 8258h SCI4.SMR 0008 8260h, SCI5.SMR 0008 8268h, SCI6.SMR 0008 8270h BCP[1:0] CKS[1:0] Value after reset: Symbol...
Page 618 RX610 Group 20. Serial Communications Interface (SCI) CKS[1:0] Bits (Clock Select) These bits select the clock source for the on-chip baud rate generator. For the relationship between the settings of these bits and the baud rate, see section 20.2.9, Bit Rate Register (BRR). BCP[1:0] Bits (Base Clock Pulse) These bits select the number of base clock cycles in a 1-bit data transfer time in smart card interface mode.
Page 619: Serial Control Register (Scr)
RX610 Group 20. Serial Communications Interface (SCI) 20.2.6 Serial Control Register (SCR) Note: Some bits in SCR have different functions in serial communications interface mode and smart card interface mode. (1) Serial Communications Interface Mode (SMIF in SCMR = 0) Address: SCI0.SCR 0008 8242h, SCI1.SCR 0008 824Ah, SCI2.SCR 0008 8252h, SCI3.SCR 0008 825Ah SCI4.SCR 0008 8262h, SCI5.SCR 0008 826Ah, SCI6.SCR 0008 8272h —...
Page 620 RX610 Group 20. Serial Communications Interface (SCI) Symbol Bit Name Function • b1, b0 CKE[1:0] Clock Enable For SCI5 and SCI6 R/W* Asynchronous mode b1 b0 0 0: On-chip baud rate generator The SCKn pin functions as I/O port. 0 1: On-chip baud rate generator The clock with the same frequency as the bit rate is output from the SCKn pin.
Page 621 RX610 Group 20. Serial Communications Interface (SCI) CKE[1:0] Bits (Clock Enable) These bits select the clock source and SCKn pin function. TEIE Bit (Transmit End Interrupt Enable) Enables or disables a TEI interrupt request. A TEI interrupt request is disabled by clearing the TEIE bit to 0. RE Bit (Receive Enable) Enables or disables serial reception.
Page 622 RX610 Group 20. Serial Communications Interface (SCI) (2) Smart Card Interface Mode (SMIF in SCMR = 1) Addresses: SCI0.SCR 0008 8242h, SCI1.SCR 0008 824Ah, SCI2.SCR 0008 8295h, SCI3.SCR 0008 25Ah SCI4.SCR 0008 8262h, SCI5.SCR 0008 826Ah, SCI6.SCR 0008 8272h — TEIE CKE[1:0] Value after reset:...
Page 623 RX610 Group 20. Serial Communications Interface (SCI) RE Bit (Receive Enable) Enables or disables serial reception. When this bit is set to 1, serial reception is started by detecting the start bit. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format.
Page 624: Serial Status Register (Ssr)
RX610 Group 20. Serial Communications Interface (SCI) 20.2.7 Serial Status Register (SSR) Note: Some bits in SSR have different functions in serial communications interface mode and smart card interface mode. (1) Serial Communications Interface Mode (SMIF in SCMR = 0) Addresses: SCI0.SSR 0008 8244h, SCI1.SSR 0008 824Ch, SCI2.SSR 0008 8254h, SCI3.SSR 0008 25Ch, SCI4.SSR 0008 8264h, SCI5.SSR 0008 826Ch, SCI6.SSR 0008 8274h —...
Page 625 RX610 Group 20. Serial Communications Interface (SCI) PER Bit (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] • When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 626 RX610 Group 20. Serial Communications Interface (SCI) RDRF Bit (Receive Data Full Flag) Indicates whether RDR has received data. [Setting condition] • When data has been received normally, and transferred from RSR to RDR [Clearing condition] • When data is transferred from RDR. TDRE Bit (Transmit Data Empty Flag) Indicates whether TDR has data to be transmitted.
Page 627 RX610 Group 20. Serial Communications Interface (SCI) (2) Smart Card Interface Mode (SMIF in SCMR = 1) Addresses: SCI0.SSR 0008 8244h, SCI1.SSR 0008 824Ch, SCI2.SSR 0008 8254h, SCI3.SSR 0008 25Ch, SCI4.SSR 0008 8264h, SCI5.SSR 0008 826Ch, SCI6.SSR 0008 8274h — —...
Page 628 RX610 Group 20. Serial Communications Interface (SCI) PER Flag (Parity Error Flag) Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] • When a parity error is detected during reception Although receive data when the parity error occurs is transferred to RDR, no RXI interrupt request occurs.
Page 629 RX610 Group 20. Serial Communications Interface (SCI) TDRE Bit (Transmit Data Empty Flag) Indicates whether TDR has data to be transmitted. [Setting condition] • When data is transferred from TDR to TSR [Clearing condition] • When data is transferred to TDR R01UH0032EJ0120 Rev.1.20 Page 629 of 1006 Feb 20, 2013...
Page 630: Smart Card Mode Register (Scmr)
RX610 Group 20. Serial Communications Interface (SCI) 20.2.8 Smart Card Mode Register (SCMR) Addresses: SCI0.SCMR 0008 8246h, SCI1.SCMR 0008 824Eh, SCI2.SCMR 0008 8256h, SCI3.SCMR 0008 25Eh SCI4.SCMR 0008 8266h, SCI5.SCMR 0008 826Eh, SCI6.SCMR 0008 8276h — — — — BCP2 SDIR SINV SMIF...
Page 631 RX610 Group 20. Serial Communications Interface (SCI) SDIR Bit (Bit Order Select) Selects the serial/parallel conversion format. BCP2 Bit (Base Clock Pulse 2) Selects the number of base clock cycles in a 1-bit data transfer time in smart card interface mode. Set this bit in combination with the BCP1 and BCP2 bits in SMR.
Page 632: Bit Rate Register (Brr)
RX610 Group 20. Serial Communications Interface (SCI) 20.2.9 Bit Rate Register (BRR) Addresses: SCI0.BRR 0008 8241h, SCI1.BRR 0008 8249h, SCI2.BRR 0008 8251h, SCI3.BRR 0008 8259h SCI4.BRR 0008 8261h, SCI5.BRR 0008 8269h, SCI6.BRR 0008 8271h Value after reset: BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel.
Page 633 RX610 Group 20. Serial Communications Interface (SCI) SCMR Setting SMR Setting BCP2 Bit BCP[1:0] bps Base Clock 93 clock cycles 128 clock cycles 186 clock cycles 512 clock cycles 32 clock cycles 64 clock cycles 372 clock cycles 256 clock cycles Tables 20.6 shows sample N settings in BRR in normal asynchronous mode.
Page 634 RX610 Group 20. Serial Communications Interface (SCI) Table 20.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency PCLK (MHz) 9.8304 Bit Rate (bps) Error (%) Error (%) Error (%) Error (%) 0.03 -0.26 -0.25 0.03 0.16 0.00 0.16...
Page 635 RX610 Group 20. Serial Communications Interface (SCI) Table 20.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency PCLK (MHz) 17.2032 19.6608 Bit Rate (bps) Error (%) Error (%) Error (%) Error (%) 0.48 -0.12 0.31 -0.25 0.00 0.16...
Page 636 RX610 Group 20. Serial Communications Interface (SCI) Table 20.7 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode) Maximum Bit Rate Maximum Bit Rate PCLK (MHz) (bps) PCLK (MHz) (bps) 250000 17.2032 537600 9.8304 307200 562500 312500 19.6608 614400 375000 625000 12.288 384000...
Page 637 RX610 Group 20. Serial Communications Interface (SCI) Table 20.9 BRR Settings for Various Bit Rates (Clock Synchronous Mode) Operating Frequency PCLK (MHz) Bit Rate (bps) 2.5k 100k 250k 500k 2.5M 6.25M 7.5M 8.25M 12.5M [Legend] Space: Setting prohibited. Can be set, but there will be error. * Continuous transmission or reception is not poss ble.
Page 638 RX610 Group 20. Serial Communications Interface (SCI) Table 20.11 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372) Operating Frequency PCLK (MHz) 7.1424 10.00 10.7136 13.00 Bit Rate (bps) Error (%) Error (%) Error (%) Error (%) 9600...
Page 639: Serial Extended Mode Register (Semr)
RX610 Group 20. Serial Communications Interface (SCI) 20.2.10 Serial Extended Mode Register (SEMR) Addresses: SCI0.SEMR 0008 8247h, SCI1.SEMR 0008 824Fh, SCI2.SEMR 0008 8257h, SCI3.SEMR 0008 825Fh SCI4.SEMR 0008 8267h, SCI5.SEMR 0008 826Fh, SCI6.SEMR 0008 8277h — — — — — —...
Page 640 RX610 Group 20. Serial Communications Interface (SCI) TMR (unit 0) SCI5 Base clock TMO0 SCK5 This figure shows an example when TMR clock is input to SCI5. TMO1 When generating 187.5 kbps of TMR average transfer rate for PCLK = 32 MHz: Clock enable (1) Generate a frequency of 4 MHz using TMO0 as the base clock.
Page 641: Operation In Asynchronous Mode
RX610 Group 20. Serial Communications Interface (SCI) 20.3 Operation in Asynchronous Mode Figure 20.4 shows the general format for asynchronous serial communications. One frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communications, the communications line is usually held in the mark state (high level).
Page 642: Serial Data Transfer Format
RX610 Group 20. Serial Communications Interface (SCI) 20.3.1 Serial Data Transfer Format Table 20.13 shows the serial data transfer formats that can be used in asynchronous mode. Any of 8 transfer formats can be selected according to the SMR setting. Table 20.13 Serial Transfer Formats (Asynchronous Mode) SMR Setting...
Page 643: Receive Data Sampling Timing And Reception Margin In Asynchronous Mode
RX610 Group 20. Serial Communications Interface (SCI) 20.3.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times* the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse* of the base clock, data is latched at the middle of each bit, as shown in figure 20.5.
Page 644: Clock
RX610 Group 20. Serial Communications Interface (SCI) 20.3.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be selected as the SCI's transfer clock, according to the setting of the CA bit in SMR and the CKE[1:0] bits in SCR. When an external clock is input to the SCKn pin, the clock frequency should be 16 times the bit rate (when ABCS in SEMR = 0) and 8 times the bit rate (when ABCS in SEMR = 1).
Page 645: Sci Initialization (Asynchronous Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.3.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, start by writing the initial value "00h" to the SCR and then continue through the procedure for SCI given in the sample flowchart (figure 20.7). Whenever the operating mode or transfer format is changed, the SCR must be initialized before the change is made.
Page 646: Serial Data Transmission (Asynchronous Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.3.5 Serial Data Transmission (Asynchronous Mode) Figure 20.8 shows an example of the operation for serial transmission in asynchronous mode. In serial transmission, the SCI operates as described below. The SCI transfers data from TDR to TSR when data is written to TDR in the TXI interrupt processing routine. The TXI interrupt request at the beginning of transmission is generated when the TE bit in SCR is set to 1 after the TIE bit in SCR is set to 1 or when these two bits are set to 1 simultaneously by a single instruction.
Page 647 RX610 Group 20. Serial Communications Interface (SCI) [ 1 ] [ 1 ] SCIn initialization: Initialization The TxDn pin is automatically designated as the transmit data output pin. After the TE bit in SCR is set to 1, a 1 is output Start data transmission for a frame, and transmission is enabled.
Page 648: Serial Data Reception (Asynchronous Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.3.6 Serial Data Reception (Asynchronous Mode) Figure 20.10 shows an example of the operation for serial data reception in asynchronous mode. In serial data reception, the SCI operates as described below. When the SCI monitors the communications line and detects a start bit, it performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit.
Page 649 RX610 Group 20. Serial Communications Interface (SCI) Table 20.14 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, an ERI interrupt request is generated but an RXI interrupt request is not generated. Data reception cannot be resumed while the receive error flag is set to 1.
Page 650 RX610 Group 20. Serial Communications Interface (SCI) [ 1 ] SCIn initialization: The RxDn pin is automatically designated as the receive data input pin. [ 1 ] Initialization [ 2 ] [ 3 ] Receive error processing and break detection: Start data reception If a receive error occurs, an ERI interrupt is generated.
Page 651 RX610 Group 20. Serial Communications Interface (SCI) [ 3 ] Error processing ORER in SSR = 1 Note: * Read the RDR register. Overrun error processing* FER in SSR = 1 Break? Framing error processing Clear RE bit in SCR to 0 PER in SSR = 1 Parity error processing Clear ORER, FER, and PER flags...
Page 652: Operation In Clock Synchronous Mode
RX610 Group 20. Serial Communications Interface (SCI) 20.4 Operation in Clock Synchronous Mode Figure 20.13 shows the data format for clock synchronous serial data communications. In clock synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data.
Page 653: Sci Initialization (Clock Synchronous Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.4.2 SCI Initialization (Clock Synchronous Mode) Before transmitting and receiving data, start by writing the initial value "00h" to the SCR and then continue through the procedure for SCI given in the sample flowchart (figure 20.14). Whenever the operating mode or transfer format is changed, the SCR must be initialized before the change is made.
Page 654: Serial Data Transmission (Clock Synchronous Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.4.3 Serial Data Transmission (Clock Synchronous Mode) Figure 20.15 shows an example of the operation for serial transmission in clock synchronous mode. In serial data transmission, the SCI operates as described below. The SCI transfers data from TDR to TSR when data is written to TDR in the TXI interrupt processing routine. The TXI interrupt request at the beginning of transmission is generated when the TE bit in SCR is set to 1 after the TIE bit in SCR is set to 1 or when these two bits are set to 1 simultaneously by a single instruction.
Page 655 RX610 Group 20. Serial Communications Interface (SCI) [ 1 ] SCIn initialization: [ 1 ] Initialization The TxDn pin is automatically designated as the transmit data output pin. Start transmission [ 2 ] Transmit data write to TDR upon accepting a TXI interrupt request: When transmit data is transferred from TDR to TSR, a transmit data empty interrupt (TXI) request is...
Page 656: Serial Data Reception (Clock Synchronous Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.4.4 Serial Data Reception (Clock Synchronous Mode) Figure 20.17 shows an example of SCI operation for serial reception in clock synchronous mode. In serial data reception, the SCI operates as described below. The SCI performs internal initialization and starts receiving data in synchronization with a synchronization clock input or output, and stores the receive data in RSR.
Page 657 RX610 Group 20. Serial Communications Interface (SCI) Initialization [ 1 ] [ 1 ] SCIn initialization: Set the port to be used as the RxDn pin to an input port. Start data reception [ 2 ] [ 3 ] Receive error processing: If a receive error occurs, read the ORER flag in SSR, [ 2 ] Read ORER flag in SSR...
Page 658: Simultaneous Serial Data (Clock Synchronous Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.4.5 Simultaneous Serial Data (Clock Synchronous Mode) Figure 20.19 shows a sample flowchart for simultaneous serial transmit and receive operations in clock synchronous mode. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations.
Page 659 RX610 Group 20. Serial Communications Interface (SCI) [ 1 ] SCI initialization: [ 1 ] Ini ialization The TxDn pin is designated as the transmit data output pin, and the RxDn pin is designated as the receive data Start data transmission/reception input pin, enabling simultaneous transmit/receive operations.
Page 660: Operation In Smart Card Interface Mode
RX610 Group 20. Serial Communications Interface (SCI) 20.5 Operation in Smart Card Interface Mode The SCI supports the smart card (IC card) interface conforming to the ISO/IEC 7816-3 (Identification Card) standard, as an extended function of the SCI. Smart card interface mode can be selected using the appropriate register. 20.5.1 Sample Connection Figure 20.20 shows a sample connection between the smart card (IC card) and this LSI.
Page 661: Data Format (Except In Block Transfer Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.5.2 Data Format (Except in Block Transfer Mode) Figure 20.21 shows the data transfer formats in smart card interface mode. • One frame consists of 8-bit data and a parity bit in asynchronous mode. •...
Page 662: Block Transfer Mode
RX610 Group 20. Serial Communications Interface (SCI) For communications with IC cards of the direct convention type and inverse convention type, follow the procedure below. (1) Direct Convention Type For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 20.22.
Page 663: Receive Data Sampling Timing And Reception Margin
RX610 Group 20. Serial Communications Interface (SCI) 20.5.4 Receive Data Sampling Timing and Reception Margin Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, 256, 93, 128, 186, or 512 times the bit rate according to the settings of the BCP2 bit in SCMR and BCP[1:0] bits in SMR (the frequency is always 16 times the bit rate in normal asynchronous mode).
Page 664 RX610 Group 20. Serial Communications Interface (SCI) 372 clock cycles 186 clock cycles 371 0 Internal base clock Start bit Receive data (RxDn) Synchronization sampling timing Data sampling timing Figure 20.24 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate) R01UH0032EJ0120 Rev.1.20 Page 664 of 1006...
Page 665: Initialization Of The Sci
RX610 Group 20. Serial Communications Interface (SCI) 20.5.5 Initialization of the SCI Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. Write the initial value "00h" to the SCR. Set the Bj bit (j = 0 to 7) in ICR of Pm (m = 0 to 9, A to E) of the corresponding pin to 1.
Page 666: Serial Data Transmission (Except In Block Transfer Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.5.6 Serial Data Transmission (Except in Block Transfer Mode) Serial data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communications interface mode in that an error signal is sampled and data can be re-transmitted. Figure 20.25 shows the data re-transfer operation during transmission.
Page 667 RX610 Group 20. Serial Communications Interface (SCI) Note that the SSR.TEND flag is set in different timings depending on the GM bit setting in SMR. Figure 20.26 shows the TEND flag generation timing. I/O data SSR.TEND flag Guard (TX interrrupt) time 12.5 etu (11.5 etu in block transfer mode) When GM bit in SMR = 0...
Page 668 RX610 Group 20. Serial Communications Interface (SCI) Start Initialization Start data transmission ERS = 0? Error processing TXI interrupt Write data to TDR All data transmitted? ERS = 0? Error processing TXI interrupt Clear bits TIE, RIE, and TE in SCR to 0 Figure 20.27 Sample Serial Transmission Flowchart R01UH0032EJ0120 Rev.1.20...
Page 669: Serial Data Reception (Except In Block Transfer Mode)
RX610 Group 20. Serial Communications Interface (SCI) 20.5.7 Serial Data Reception (Except in Block Transfer Mode) Serial data reception in smart card interface mode is similar to that in serial communications interface mode. Figure 20.28 shows the data retransfer operation in reception mode. If a parity error is detected in receive data, the PER flag in SSR is set to 1.
Page 670: Clock Output Control
RX610 Group 20. Serial Communications Interface (SCI) Start Initialization Start data reception ORER = 0 and PER = 0? Error processing RXI interrupt Read data from RDR All data received? Clear bits RIE and RE in SCR to 0 Figure 20.29 Sample Serial Reception Flowchart 20.5.8 Clock Output Control...
Page 671 RX610 Group 20. Serial Communications Interface (SCI) (1) At Power-On To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor.
Page 672: Interrupt Sources
RX610 Group 20. Serial Communications Interface (SCI) 20.6 Interrupt Sources 20.6.1 Interrupts in Serial Communications Interface Mode Table 20.15 lists interrupt sources in normal serial communications interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled with the enable bits in SCR. Transfer of data from the transmit data register (TDR) to the TSR while the SCR.TIE bit is 1 leads to the generation of a TXI interrupt request.
Page 673: Interrupts In Smart Card Interface Mode
RX610 Group 20. Serial Communications Interface (SCI) 20.6.2 Interrupts in Smart Card Interface Mode Table 20.16 lists interrupt sources in smart card interface mode. A transmit end interrupt (TEI) request cannot be used in this mode. Table 20.16 SCI Interrupt Sources Name Interrupt Source Interrupt Flag...
Page 674: Usage Notes
RX610 Group 20. Serial Communications Interface (SCI) 20.7 Usage Notes 20.7.1 Setting the Module Stop Function Operation of the SCI can be disabled or enabled using the module stop control register B (MSTPCRB). The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing the module stop state. For details, see section 8, Low Power Consumption.
Page 675: Restrictions On Clock Synchronous Transmission
RX610 Group 20. Serial Communications Interface (SCI) 20.7.6 Restrictions on Clock Synchronous Transmission When the external clock source is used as a synchronization clock, update TDR by the DMAC or DTC and wait for at least five clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR is updated, the SCI may malfunction.
Page 676 RX610 Group 20. Serial Communications Interface (SCI) <Data transmission> [ 1 ] Data being transmitted is lost halfway. Data can be [ 1 ] All data transmitted? normally transmitted from the CPU by setting the TE bit in SCR to 1, reading SSR, and writing data to TDR after canceling software standby mode.
Page 677 RX610 Group 20. Serial Communications Interface (SCI) Transition to software standby Software standby Transmission end Transmission start mode mode canceled SCR.TE bit Port input/output SCKn output pin TxDn output pin High output* Port input/output Marking output Last TxD bit retained Port input/output Port SCI TxDn output...
Page 678: External Clock Input In Clock Synchronous Mode
RX610 Group 20. Serial Communications Interface (SCI) 20.7.9 External Clock Input in Clock Synchronous Mode In clock synchronous mode, the external clock SCKn must be input as follows: High-pulse period, low-pulse period = 2 clock cycles or more, period = 6 clock cycles or more R01UH0032EJ0120 Rev.1.20 Page 678 of 1006 Feb 20, 2013...
Page 679: Overview
RX610 Group 21. CRC Calculator (CRC) CRC Calculator (CRC) The CRC (Cyclic Redundancy Check) calculator generates CRC codes of data blocks. 21.1 Overview Table 21.1 lists the specifications of the CRC calculator, and figure 21.1 shows a block diagram of the CRC calculator. Table 21.1 Specifications of CRC Item...
Page 680: Register Descriptions
RX610 Group 21. CRC Calculator (CRC) 21.2 Register Descriptions Table 21.2 lists the registers of the CRC calculator. Table 21.2 Registers of CRC Calculator Register Name Symbol Value after Reset Address Access Size CRC control register CRCCR 0008 8280h CRC data input register CRCDIR 0008 8281h CRC data output register...
Page 681: Crc Data Input Register (Crcdir)
RX610 Group 21. CRC Calculator (CRC) DORCLR Bit (CRCDOR Register Clear) Write 1 to this bit so that the CRCDOR register is cleared to 0000h. This bit is always read as 0. 21.2.2 CRC Data Input Register (CRCDIR) Address: 0008 8281h Value after reset: CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written.
Page 682: Operation
RX610 Group 21. CRC Calculator (CRC) 21.3 Operation The CRC calculator generates CRC codes for use in LSB-first or MSB-first transfer. The following figures show examples in which the CRCCR.GPS[1:0] bits are set to 11b so the CRC code is calculated by using a 16-bit CRC (with the polynomial X + 1), and the CRC code is calculated for the value "F0h".
Page 683 RX610 Group 21. CRC Calculator (CRC) 1. Serial reception (LSB first) CRC code Data Input 2. Write 83h to CRCCR CRCCR CRCDOR Clear CRCDOR 3. Write F0h to CRCDIR CRCDIR CRCDOR CRC code generation 4. Write 8Fh to CRCD CRCDIR CRCDOR CRC code generation 5.
Page 684 RX610 Group 21. CRC Calculator (CRC) 1. Serial reception (MSB first) CRC code Data Input 2. Write 87h to CRCCR CRCCR CRCDOR Clear CRCDOR 3. Write F0h to CRCDIR CRCDIR CRCDOR CRC code generation 4. Write EFh to CRCD CRCDIR CRC code generation 5.
Page 685: Usage Notes
RX610 Group 21. CRC Calculator (CRC) 21.4 Usage Notes 21.4.1 Module Stop Function Setting Operation of the CRC calculator can be disabled or enabled using the module stop control register B (MSTPCRB). The initial setting is for operation of the CRC calculator to be halted. Register access is enabled by clearing the module stop state.
Page 686: Overview
RX610 Group 22. I C Bus Interface (RIIC) C Bus Interface (RIIC) The RX610 Group has two I C bus interfaces (RIIC modules). The RIIC module conforms with and provides a subset of the NXP I C bus (inter-IC bus) interface functions. 22.1 Overview Table 22.1 lists the specifications of the RIIC, figure 22.1 shows a block diagram of the RIIC, and figure 22.2 shows an...
Page 687 RX610 Group 22. I C Bus Interface (RIIC) Item Specifications • Timeout detection function The internal timeout detection function is capable of detecting long-interval stoppages of the SCL (clock signal). • Noise removal The interface incorporates digital noise filters for both the SCL and SDA signals, and the width for noise cancellation by the filters is adjustable.
Page 688 RX610 Group 22. I C Bus Interface (RIIC) PCLK CKS[2 0] ICMR1 BC[2 0] FMPE IICφ (PCLK/1 to PCLK/128) Output ICBRH SCLn Transfer clock control generator ICBRL SCLE Noise SCLI canceler ICCR1 SCL0, SDA0 NF[1 0] IICRST SDAI Transmission/rece ST, RS, SP ption control circuit ICCR2 DLCS...
Page 689 RX610 Group 22. I C Bus Interface (RIIC) SCLin SCLout# SDAin SDAout# (Master) SCLin SCLin SCLout# SCLout# SDAin SDAin SDAout# SDAout# (Slave 1) (Slave 2) Figure 22.2 Connections to the External Circuit by the I/O Pins (I C Bus Configuration Example) Table 22.2 Pin Configuration Channel...
Page 690: Register Descriptions
RX610 Group 22. I C Bus Interface (RIIC) 22.2 Register Descriptions Table 22.3 lists the registers of the RIIC. Table 22.3 Registers of the RIIC Channel Register Name Symbol Value after Reset Address Access Size RIIC0 C bus control register 1 ICCR1 0008 8300h C bus control register 2...
Page 691 RX610 Group 22. I C Bus Interface (RIIC) Channel Register Name Symbol Value after Reset Address Access Size   RIIC1 C bus shift register ICDRS R01UH0032EJ0120 Rev.1.20 Page 691 of 1006 Feb 20, 2013...
Page 692 RX610 Group 22. I C Bus Interface (RIIC) 22.2.1 C Bus Control Register 1 (ICCR1) Addresses: RIIC0.ICCR1 0008 8300h, RIIC1.ICCR1 0008 8320h IICRST SOWP SCLO SDAO SCLI SDAI Value after reset: Symbol Bit Name Description SDAI SDA Bus Input Monitor 0: SDAn pin input is at a low level 1: SDAn pin input is at a high level SCLI...
Page 693 RX610 Group 22. I C Bus Interface (RIIC) ICCR1 enables or disables the RIIC, resets the internal state of the RIIC, outputs an extra SCL clock cycle, and manipulates and monitors the SCLn pin and SDAn pin. SDAI Bit (SDA Bus Input Monitor) This bit indicates the input level of the SDAn pin.
Page 694 RX610 Group 22. I C Bus Interface (RIIC) Note: If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information).
Page 695 RX610 Group 22. I C Bus Interface (RIIC) 22.2.2 C Bus Control Register 2 (ICCR2) Addresses: RIIC0.ICCR2 0008 8301h, RIIC1.ICCR2 0008 8321h — — BBSY Value after reset: Symbol Bit Name Description  Reserved This bit is always read as 0. The write value should always be 0. Start Condition Issuance Request 0: Does not request to issue a start condition 1: Requests to issue a start condition...
Page 696 RX610 Group 22. I C Bus Interface (RIIC) RS Bit (Restart Condition Issuance Request) This bit is used to request that a restart condition be issued in master mode. When this bit is set to 1 to request to issue a restart condition, a restart condition is issued when the BBSY flag is set to 1 (bus busy) and the MST bit is set to 1 (master mode).
Page 697 RX610 Group 22. I C Bus Interface (RIIC) TRS Bit (Transmit/Receive Mode) This bit indicates transmit or receive mode. The RIIC is in receive mode when the TRS bit is set to 0 and is in transmit mode when the bit is set to 1. Combination of this bit and the MST bit indicates the operating mode of the RIIC.
Page 698 RX610 Group 22. I C Bus Interface (RIIC) BBSY Flag (Bus Busy Detection) The BBSY flag indicates whether the I C bus is occupied (bus busy) or released (bus free). This bit is set to 1 when the SDAn line changes from high to low under the condition of SCLn = high, assuming that a start condition has been issued.
Page 699 RX610 Group 22. I C Bus Interface (RIIC) 22.2.3 C Bus Mode Register 1 (ICMR1) Addresses: RIIC0.ICMR1 0008 8302h, RIIC1.ICMR1 0008 8322h MTWP CKS[2:0] BCWP BC[2:0] Value after reset: Symbol Bit Name Description b2 to b0 BC[2:0] Bit Counter* b2 b1 b0 R/W* 0 0 0: 9 bits 0 0 1: 2 bits...
Page 700 RX610 Group 22. I C Bus Interface (RIIC) BCWP Bit (BC Write Protect) This bit enables a value to be written in the BC[2:0] bits. CKS[2:0] Bits (Internal Reference Clock Selection) These bits select a reference clock source (IICφ) inside the RIIC. MTWP Bit (MST/TRS Write Protect) This bit controls the modification of the MST and TRS bits in ICCR2.
Page 701 RX610 Group 22. I C Bus Interface (RIIC) 22.2.4 C Bus Mode Register 2 (ICMR2) Addresses: RIIC0.ICMR2 0008 8303h, RIIC1.ICMR2 0008 8323h DLCS SDDL[2:0] TMWE TMOH TMOL TMOS Value after reset: Symbol Bit Name Description TMOS Timeout Detection Time Selection 0: Long mode is selected 1: Short mode is selected TMOL...
Page 702 RX610 Group 22. I C Bus Interface (RIIC) TMOS Bit (Timeout Detection Time Selection) This bit is used to select long mode or short mode for the timeout detection time when the timeout detection function is enabled (TMOE bit = 1 in ICFER). When this bit is set to 0, long mode is selected. When this bit is set to 1, short mode is selected.
Page 703 RX610 Group 22. I C Bus Interface (RIIC) 22.2.5 C Bus Mode Register 3 (ICMR3) Addresses: RIIC0.ICMR3 0008 8304h, RIIC1.ICMR3 0008 8324h NF[1:0] SMBS WAIT RDRFS ACKWP ACKBT ACKBR Value after reset: Symbol Bit Name Description b1, b0 NF[1:0] Noise Filter Stage Selection b1 b0 0 0: Noise of up to 1-PCLK range is filtered out (single-stage filter) 0 1: Noise of up to 2-PCLK range is filtered out (2-stage filter)
Page 704 RX610 Group 22. I C Bus Interface (RIIC) NF[1:0] Bits (Noise Filter Stage Selection) These bits are used to select the number of stages of the digital noise filter. Note: Set the noise range to be filtered out by the noise filter within a range less than the SCLn line high-level period or low-level period.
Page 705 RX610 Group 22. I C Bus Interface (RIIC) WAIT Bit (WAIT) This bit is used to control whether to hold the period between the ninth SCL clock cycle and the first SCL clock cycle low until the receive data buffer (ICDRR) is completely read each time single-byte data is received in receive mode. When the WAIT bit is 0, the receive operation is continued without holding the period between the ninth and the first SCL clock cycle low.
Page 706 RX610 Group 22. I C Bus Interface (RIIC) 22.2.6 C Bus Function Enable Register (ICFER) Addresses: RIIC0.ICFER 0008 8305h, RIIC1.ICFER 0008 8325h FMPE SCLE NACKE SALE NALE MALE TMOE Value after reset: Symbol Bit Name Description TMOE Timeout Detection Function Enable 0: The timeout detection function is disabled 1: The timeout detection function is enabled MALE...
Page 707 RX610 Group 22. I C Bus Interface (RIIC) NALE Bit (NACK Transmission Arbitration Lost Detection Enable) This bit is used to specify whether to cause arbitration to be lost when ACK is detected during transmission of NACK in receive mode (such as when slaves with the same address exist on the bus or when two or more masters select the same slave device simultaneously with different number of receive bytes).
Page 708 RX610 Group 22. I C Bus Interface (RIIC) 22.2.7 C Bus Status Enable Register (ICSER) Addresses: RIIC0.ICSER 0008 8306h, RIIC1.ICSER 0008 8326h — — HOAE DIDE GCAE SAR2E SAR1E SAR0E Value after reset: Symbol Bit Name Description SAR0E Slave Address Register 0 Enable 0: Slave address in SARL0 and SARU0 is disabled 1: Slave address in SARL0 and SARU0 is enabled SAR1E...
Page 709 RX610 Group 22. I C Bus Interface (RIIC) GCAE Bit (General Call Address Enable) This bit is used to specify whether to ignore the general call address (0000 000b + 0 [W]: All 0) when it is received. When this bit is set to 1, if the received slave address matches the general call address, the RIIC recognizes the received slave address as the general call address independently of the slave addresses set in SARLy and SARUy (y = 0 to 2) and performs data receive operation.
Page 710 RX610 Group 22. I C Bus Interface (RIIC) 22.2.8 C Bus Interrupt Enable Register (ICIER) Addresses: RIIC0.ICIER 0008 8307h, RIIC1.ICIER 0008 8327h TEIE NAKIE SPIE STIE ALIE TMOIE Value after reset: Symbol Bit Name Description TMOIE Timeout Interrupt Enable 0: Timeout interrupt request (TMOI) is disabled 1: Timeout interrupt request (TMOI) is enabled ALIE Arbitration Lost Interrupt Enable...
Page 711 RX610 Group 22. I C Bus Interface (RIIC) SPIE Bit (Stop Condition Detection Interrupt Enable) This bit is used to enable or disable stop condition detection interrupt requests (SPI) when the STOP flag in ICSR2 is set to 1. An SPI interrupt request is canceled by clearing the STOP flag or the SPIE bit to 0. NAKIE Bit (NACK Reception Interrupt Enable) This bit is used to enable or disable NACK reception interrupt requests (NAKI) when the NACKF flag in ICSR2 is set to 1.
Page 712 RX610 Group 22. I C Bus Interface (RIIC) 22.2.9 C Bus Status Register 1 (ICSR1) Addresses: RIIC0.ICSR1 0008 8308h, RIIC1.ICSR1 0008 8328h — — AAS2 AAS1 AAS0 Value after reset: Symbol Bit Name Description AAS0 Slave Address 0 Detection Flag 0: Slave address 0 is not detected R/(W) 1: Slave address 0 is detected...
Page 713 RX610 Group 22. I C Bus Interface (RIIC) Symbol Bit Name Description Device-ID Command Detection Flag 0: Device-ID command is not detected R/(W) 1: Device-ID command is detected • This bit is set to 1 when the first frame received immediately after a start condition is detected matches a value of (device ID (1111 100b) + 0 [W]).
Page 714 RX610 Group 22. I C Bus Interface (RIIC) GCA Flag (General Call Address Detection) [Setting condition] • When the received slave address matches the general call address (0000 000b + 0 [W]) with the GCAE bit in ICSER set to 1 (general call address detection enabled) This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the frame.
Page 715 RX610 Group 22. I C Bus Interface (RIIC) HOA Flag (Host Address Detection) [Setting condition] • When the received slave address matches the host address (0001 000b) with the HOAE bit in ICSER set to 1 (host address detection enabled) This flag is set to 1 at the rising edge of the ninth SCL clock cycle in the frame.
Page 716 RX610 Group 22. I C Bus Interface (RIIC) 22.2.10 I C Bus Status Register 2 (ICSR2) Addresses: RIIC0.ICSR2 0008 8309h, RIIC1.ICSR2 0008 8329h TDRE TEND RDRF NACKF STOP START TMOF Value after reset: Symbol Bit Name Description TMOF Timeout Detection Flag 0: Timeout is not detected R/(W) 1: Timeout is detected...
Page 717 RX610 Group 22. I C Bus Interface (RIIC) AL Flag (Arbitration Lost Flag) This flag shows that bus mastership has been lost (loss in arbitration) due to a bus conflict or some other reason when a start condition is issued or an address and data are transmitted. The RIIC monitors the level on the SDAn line during transmission and, if the level on the line does not match the value of the bit being output, sets the value of the AL bit to 1 to indicate that the bus is occupied by another device.
Page 718 RX610 Group 22. I C Bus Interface (RIIC) START Flag (Start Condition Detection) [Setting condition] • When a start condition (or a restart condition) is detected [Clearing conditions] • When 0 is written to the START bit after reading START = 1 •...
Page 719 RX610 Group 22. I C Bus Interface (RIIC) TEND Flag (Transmit End) [Setting condition] • At the rising edge of the ninth SCL clock cycle while the TDRE flag is 1 [Clearing conditions] • When 0 is written to the TEND bit after reading TEND = 1 •...
Page 720: Slave Address Register Ly (Sarly) (Y = 0 To 2)
RX610 Group 22. I C Bus Interface (RIIC) 22.2.11 Slave Address Register Ly (SARLy) (y = 0 to 2) Addresses: RIIC0.SARL0 0008 830Ah, RIIC1.SARL0 0008 832Ah RIIC0.SARL1 0008 830Ch, RIIC1.SARL1 0008 832Ch RIIC0.SARL2 0008 830Eh, RIIC1.SARL2 0008 832Eh SVA0 SVA[7:1] Value after reset: Symbol Bit Name...
Page 721: Slave Address Register Uy (Saruy) (Y = 0 To 2)
RX610 Group 22. I C Bus Interface (RIIC) 22.2.12 Slave Address Register Uy (SARUy) (y = 0 to 2) Addresses: RIIC0.SARU0 0008 830Bh, RIIC1.SARU0 0008 832Bh RIIC0.SARU1 0008 830Dh, RIIC1.SARU1 0008 832Dh RIIC0.SARU2 0008 830Fh, RIIC1.SARU2 0008 832Fh SVA[9:8] — —...
Page 722 RX610 Group 22. I C Bus Interface (RIIC) 22.2.13 I C Bus Bit Rate Low-Level Register (ICBRL) Addresses: RIIC0.ICBRH 0008 8310h, RIIC1.ICBRH 0008 8330h — — — BRL[4:0] Value after reset: Symbol Bit Name Description b4 to b0 BRL[4:0] Bit Rate Low-Level Period Low-level period of SCL clock ...
Page 723 RX610 Group 22. I C Bus Interface (RIIC) 22.2.14 I C Bus Bit Rate High-Level Register (ICBRH) Addresses: RIIC0.ICBRL 0008 8311h, RIIC1.ICBRL 0008 8331h — — — BRH[4:0] Value after reset: Symbol Bit Name Description b4 to b0 BRH[4:0] Bit Rate High-Level Period High-level period of SCL clock ...
Page 724 RX610 Group 22. I C Bus Interface (RIIC) Table 22.6 shows examples of ICBRH/ICBRL settings. Table 22.6 Examples of ICBRH/ICBRL Settings for Transfer Rate Operating Frequency PCLK (MHz) Transfer 12.5 Rate (kbps) [2:0] ICBRH ICBRL [2:0] ICBRH ICBRL [2:0] ICBRH ICBRL 100b 22 (F6h)
Page 725 RX610 Group 22. I C Bus Interface (RIIC) 22.2.15 I C Bus Transmit Data Register (ICDRT) Addresses: RIIC0.ICDRT 0008 8312h, RIIC1.ICDRT 0008 8332h Value after reset: ICDRT is an 8-bit readable/writable register that stores transmit data. When ICDRT detects a space in the I C bus shift register (ICDRS), it transfers the transmit data that has been written to ICDRT to ICDRS and starts transmitting data in transmit mode.
Page 726: Internal Counter For Timeout (Tmocnt)
RX610 Group 22. I C Bus Interface (RIIC) 22.2.18 Internal Counter for Timeout (TMOCNT) Addresses: RIIC0.TMOCNTL 0008 830Ah, RIIC0.TMOCNTU 0008 830Bh* RIIC1.TMOCNTL 0008 832Ah, RIIC1.TMOCNTU 0008 832Bh* ICMR2.TMOS = 0 (when long mode is selected) TMOCNTU TMOCNTL Value after reset: ICMR2.TMOS = 1 (when short mode is selected) TMOCNTU TMOCNTL...
Page 727: Operation
RX610 Group 22. I C Bus Interface (RIIC) 22.3 Operation 22.3.1 Communication Data Format The I C bus format consists of 8-bit data and 1-bit acknowledge. The frame following a start condition or restart condition is an address frame used to specify a slave device with which the master device communicates. The specified slave is valid until a new slave is specified or a stop condition is issued.
Page 728: Initial Settings
RX610 Group 22. I C Bus Interface (RIIC) 22.3.2 Initial Settings Before starting data transmission and reception, initialize the RIIC according to the procedure in figure 22.5. Initial settings Clear ICE in ICCR1 to 0 RIIC function disabled Set IICRST in ICCR1 to 1 RIIC internal reset Clear IICRST in ICCR1 to 0 Cancel RIIC internal reset...
Page 729: Master Transmitter Operation
RX610 Group 22. I C Bus Interface (RIIC) 22.3.3 Master Transmitter Operation In master transmitter operation, the RIIC outputs the SCL (clock) and transmitted data signals as the master device, and the slave device returns acknowledgements. Figure 22.6 shows an example of usage of master transmission and figures 22.7 to 22.9 show the timing of operations in master transmission.
Page 730 RX610 Group 22. I C Bus Interface (RIIC) Master transmission [1] Initial settings Initial settings ICCR2.BBSY = 0? [2] Check I C bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.NACKF = 0? ICSR2.TDRE = 1? [3] Transmit slave address and W (first byte). [4] Check ACK and set transmit data.
Page 731 RX610 Group 22. I C Bus Interface (RIIC) Automatic low-hold (to prevent wrong transmission) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + W) Transmit data (DATA1) Transmit data (DATA2) TDRE TEND RDRF ICDRT 7-bit address + W DATA 1 DATA 2...
Page 732 RX610 Group 22. I C Bus Interface (RIIC) SCLn SDAn A/NA DATA n-2 DATA n-1 DATA n BBSY Transmit data (DATA n) Transmit data (DATA n-1) TDRE TEND RDRF DATA n-1 ICDRT DATA n ICDRS DATA n-2 DATA n-1 DATA n XXXX (Initial value/final receive data) ICDRR "0"...
Page 733: Master Receiver Operation
RX610 Group 22. I C Bus Interface (RIIC) 22.3.4 Master Receiver Operation In master receiver operation, the RIIC as a master device outputs the SCL (clock) signal, receives data from the slave device, and returns acknowledgements. Since the RIIC must start by sending a slave address to the corresponding slave device, this part of the procedure is performed in master transmitter mode, but the subsequent steps are in master receiver mode.
Page 734 RX610 Group 22. I C Bus Interface (RIIC) 5. After one byte of data has been received, the RDRF flag in ICSR2 is set to 1 on the rising edge of the eighth or ninth cycle of SCL clock (the clock signal) as selected by the RDRFS bit in ICMR3. Reading out ICDRR at this time will produce the received data, and the RDRF flag is automatically cleared to 0 at the same time.
Page 735 RX610 Group 22. I C Bus Interface (RIIC) Master reception Initial settings [1] Initial settings ICCR2.BBSY = 0? [2] Check I C bus occupation and issue a start condition. ICCR2.ST = 1 ICSR2.TDRE = 1? TMOCNT = 0000h Write data to ICDRT [3] Transmit slave address and R and check ACK.
Page 736 RX610 Group 22. I C Bus Interface (RIIC) Automatic low hold Master transmit mode Master receive mode (error transmission protected) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (7-bit address + R) TDRE Receive data (7-bit address + R) Receive data (DATA 1) TEND RDRF...
Page 737 RX610 Group 22. I C Bus Interface (RIIC) Automatic low hold (WAIT) Automatic low hold (error transmission protected) SCLn NACK SDAn DATA n DATA n-2 DATA n-1 BBSY TDRE Receive data (DATA n-2) Receive data (DATA n-1) Receive data (DATA n) TEND RDRF XXXX (last data for transmission [7-bit addresses + R/Upper 10 bits + R])
Page 738: Slave Transmitter Operation
RX610 Group 22. I C Bus Interface (RIIC) 22.3.5 Slave Transmitter Operation In slave transmitter operation, the master device outputs the SCL (clock) signal, the RIIC transmits data as a slave device, and the master device returns acknowledgements. Figure 22.14 shows an example of usage of slave transmission and figures 22.15 and 22.16 show the timing of operations in slave transmission.
Page 739 RX610 Group 22. I C Bus Interface (RIIC) Slave transmission [1] Initial settings Initial settings ICSR2.NACKF=0? ICSR2.TDRE=1? TMOCNT = 0000h [2], [3] Check ACK and set transmit data (Checking of ACK not necessary immediately after address is received) Write data to ICDRT All data transmitted? ICSR2.TEND=1? TMOCNT = 0000h...
Page 740 RX610 Group 22. I C Bus Interface (RIIC) Slave receive mode Slave transmit mode Automatic low hold (error transmission protected) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY Transmit data (DATA 1) Transmit data (DATA 2) TDRE TEND RDRF AASn XXXX (Initial value/last data for reception)
Page 741: Slave Receiver Operation
RX610 Group 22. I C Bus Interface (RIIC) 22.3.6 Slave Receiver Operation In slave receiver operation, the master device outputs the SCL clock and data, and the RIIC returns acknowledgements as a slave device. Figure 22.17 shows an example of usage of slave reception and figures 22.18 and 22.19 show the timing of operations in slave reception.
Page 742 RX610 Group 22. I C Bus Interface (RIIC) Slave reception Initial settings [1] Initial settings ICSR2.STOP = 0? ICSR2.RDRF = 1? ICSR2.RDRF = 1? [2], [3], [4] Read receive data (Dummy read first) TMOCNT = 0000h TMOCNT = 0000h Read ICDRR Read ICDRR (last data) All data received? ICSR2.STOP = 1?
Page 743 RX610 Group 22. I C Bus Interface (RIIC) Automatic low hold (error transmission protected) SCLn SDAn 7-bit slave address DATA 1 DATA 2 BBSY TDRE Receive data (7-bit address + W) Receive data (DATA 1) TEND RDRF AASn ICDRT XXXX (Initial value/last data for transmission) ICDRS 7-bit address + W DATA 1...
Page 744: Scl Synchronization Circuit
RX610 Group 22. I C Bus Interface (RIIC) 22.4 SCL Synchronization Circuit In generation of the SCL (clock) signal, the RIIC starts counting out the value for width at high level specified in ICBRH when it detects a rising edge on the SCLn line and drives the SCLn line low once counting of the width at high level is complete.
Page 745: Facility For Delaying Sda Output
RX610 Group 22. I C Bus Interface (RIIC) 22.5 Facility for Delaying SDA Output The RIIC module incorporates a facility for delaying output on the SDA line. The delay can be applied to all output (issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals) on the SDA line. With the SDA output delay facility, SDA output is delayed from detection of a falling edge of the SCL signal to ensure that the SDA signal is output within the interval over which the SCL (clock) signal is at the low level.
Page 746: Digital Noise-Filter Circuits
RX610 Group 22. I C Bus Interface (RIIC) 22.6 Digital Noise-Filter Circuits The states of the SCLn and SDAn pins are conveyed to the internal circuitry through analog noise-filter and digital noise-filter circuits. Figure 22.22 is a block diagram of the digital noise-filter circuit. The on-chip digital noise-filter circuit of the RIIC consists of four flip-flop circuit stages connected in series and a match-detection circuit.
Page 747: Address Match Detection
RX610 Group 22. I C Bus Interface (RIIC) 22.7 Address Match Detection The RIIC can set three unique slave addresses in addition to the general call address and host address, and also can set 7-bit or 10-bit slave addresses. 22.7.1 Slave-Address Match Detection The RIIC can set three unique slave addresses, and has a slave address detection function for each unique slave address.
Page 748 RX610 Group 22. I C Bus Interface (RIIC) [10-bit address format: Slave reception] SCLn Upper 2 bits 10-bit slave address (lower 8 bits) Data SDAn BBSY Address match AASn Receive data (lower addresses) TDRE RDRF Read ICDRR (Dummy read [lower addresses]) [10-bit address format: Slave transmission] 1 to 8 SCLn...
Page 749: Detection Of The General Call Address
RX610 Group 22. I C Bus Interface (RIIC) 22.7.2 Detection of the General Call Address The RIIC has a facility for detecting the general call address (0000 000b + 0 [W]). This is enabled by setting the GCAE bit in ICSER to 1. If the address received after a start or restart condition is issued is 0000 000b + 1[R] (start byte), the RIIC recognizes this as the address of a slave device with an "all-zero"...
Page 750: Device-Id Address Detection
RX610 Group 22. I C Bus Interface (RIIC) 22.7.3 Device-ID Address Detection The RIIC module has a facility for detecting device-ID addresses conformant with the I C bus specification (Rev. 03). When the RIIC receives 1111 100b as the first byte after a start condition or restart condition was issued with the DIDE bit in ICSER set to 1, the RIIC recognizes the address as a device ID, sets the DID flag in ICSR1 to 1 on the rising edge of the ninth SCL clock cycle when the following R/W# bit is 0, and then compares the second and subsequent bytes with its own slave address.
Page 751 RX610 Group 22. I C Bus Interface (RIIC) [Device-ID reception] SCLn Address SDAn BBSY Address match AASn Device-ID match (1111 100b + R) Device-ID match (1111 100b + W) Receive data (7-bit address/lower 10 bits) TDRE RDRF Read ICDRR (Dummy read [7-bit address/lower 10 bits]) [When address received after a restart condition is detected does not match the Device-ID] SCLn 7-bit slave address (other station)
Page 752: Host Address Detection
RX610 Group 22. I C Bus Interface (RIIC) 22.7.4 Host Address Detection The RIIC has a function to detect the host address while the SMBus is operating. When the HOAE bit in ICSER is set to 1 while the SMBS bit in ICMR3 is 1, the RIIC can detect the host address (0001 000b) in slave receive mode (MST and TRS bits = 00b in ICCR2).
Page 753: Function To Automatically Hold Scln Clock Low
RX610 Group 22. I C Bus Interface (RIIC) 22.8 Function to Automatically Hold SCLn Clock Low 22.8.1 Function to Prevent Wrong Transmission of Transmit Data If the shift register (ICDRS) is empty when data have not been written to the transmit data register (ICDRT) with the RIIC in transmission mode (TRS bit = 1 in ICCR2), the SCLn signal is automatically held at the low level over the intervals shown below.
Page 754: Nack Reception Transfer Suspension Function
RX610 Group 22. I C Bus Interface (RIIC) 22.8.2 NACK Reception Transfer Suspension Function The RIIC has a function to suspend transfer operation when NACK is received in transmit mode (TRS bit = 1 in ICCR2). This function is enabled when the NACKE bit in ICFER is set to 1 (transfer suspension enabled). If the next transmit data has already been written (TDRE flag = 0 in ICSR2) when NACK is received, next data transmission at the falling edge of the ninth SCL clock cycle is automatically suspended.
Page 755: Function To Prevent Failure To Receive Data
RX610 Group 22. I C Bus Interface (RIIC) 22.8.3 Function to Prevent Failure to Receive Data If response processing is delayed when receive data (ICDRR) read is delayed for a period of one transfer frame or more with receive data full (RDRF flag = 1 in ICSR2) in receive mode (TRS = 0 in ICCR2), the RIIC holds the SCLn line low automatically immediately before the next data is received to prevent failure to receive data.
Page 756 RX610 Group 22. I C Bus Interface (RIIC) Automatic low-hold [RDRFS = 0, WAIT = 0] (to prevent failure to receive data) SCLn Data Data Data SDAn RDRF Read ICDRR Read ICDRR Read ICDRR [RDRFS = 0, WAIT = 1] Automatic low-hold Automatic low-hold (WAIT) Automatic low-hold (WAIT)
Page 757: Arbitration-Lost Detection Functions
RX610 Group 22. I C Bus Interface (RIIC) 22.9 Arbitration-Lost Detection Functions In addition to the normal arbitration-lost detection function defined by the I C bus standard, the RIIC has functions to prevent double-issue of a start condition, to detect arbitration during transmission of NACK, and to detect arbitration in slave transmit mode.
Page 758 RX610 Group 22. I C Bus Interface (RIIC) [When slave addresses conflict] Transmit data mismatch Release SCLn/SDA (Arbitration lost) SCLn SDAn SCLn Data SDAn Data BBSY Address match Address mismatch AASn TDRE Clear AL to 0 [When data transmission conflicts after general call address is sent] Transmit data mismatch Release SCLn/SDA (Arbitration lost)
Page 759: Function To Detect Loss Of Arbitration During Nack Transmission (Nale Bit)
RX610 Group 22. I C Bus Interface (RIIC) 22.9.2 Function to Detect Loss of Arbitration during NACK Transmission (NALE Bit) The RIIC has a function to cause arbitration to be lost if the internal SDA output level does not match the level on the SDAn line (the high output as the internal SDA output;...
Page 760: Slave Arbitration Lost Detection (Sale Bit)
RX610 Group 22. I C Bus Interface (RIIC) The RIIC detects arbitration lost during transmission of NACK when the following condition is met with the NALE bit in ICFER set to 1 (arbitration lost detection during NACK transmission enabled). [Condition for arbitration lost during NACK transmission] •...
Page 761: Start Condition/Restart Condition/Stop Condition Issuing Function
RX610 Group 22. I C Bus Interface (RIIC) 22.10 Start Condition/Restart Condition/Stop Condition Issuing Function 22.10.1 Issuing a Start Condition The RIIC issues a start condition when the ST bit in ICCR2 is set to 1. When the ST bit is set to 1, a start condition issuance request is made and the RIIC issues a start condition when the BBSY flag in ICCR2 is 0 (bus free).
Page 762: Issuing A Stop Condition
RX610 Group 22. I C Bus Interface (RIIC) [Start condition issuing operation] [Restart condition issuing operation] Hold time Setup time Hold time ICBRH ICBRL ICBRH ICBRL ICBRL ICBRH ICBRL SCLn SCLn Issue start Issue restart condition condition ACK/NACK SDAn SDAn IICφ...
Page 763: Bus Hanging
RX610 Group 22. I C Bus Interface (RIIC) 22.11 Bus Hanging If the clock signals from the master and slave devices go out of synchronization due to noise or other factors, the I C bus might hang with a fixed level on the SCLn line and/or SDAn line. As measures against the bus hanging, the RIIC has a timeout detection function to detect hanging by monitoring the SCLn line, a function for the output of an extra SCL clock cycle to release the bus from a hung state due to clock signals being out of synchronization, and the RIIC/internal reset function.
Page 764 RX610 Group 22. I C Bus Interface (RIIC) [Timeout detection function] Start internal counter Start counter Start counter Start counter Start counter Start counter Clear internal counter Clear counter Clear counter Clear counter Clear counter Clear counter Clear counter SCLn SDAn IICf BBSY...
Page 765: Extra Scl Clock Cycle Output Function
RX610 Group 22. I C Bus Interface (RIIC) 22.11.2 Extra SCL Clock Cycle Output Function In master mode, the RIIC module has a facility for the output of extra SCL (clock) cycles to release the SDAn line of the slave device from being held at the low level due to the master being out of synchronization with the slave device. This function is mainly used in master mode to release the SDAn line of the slave device from the state of being fixed to the low level by including extra cycles of SCLn output from the RIIC with single cycles of the SCL (clock) signal as the unit in the case of a bus error where the RIIC cannot issue a stop condition because the slave device is holding the SDAn...
Page 766: Riic Reset And Internal Reset
RX610 Group 22. I C Bus Interface (RIIC) 22.11.3 RIIC Reset and Internal Reset The RIIC module incorporates a function for resetting itself. There are two types of reset. One is referred to as an RIIC reset; this initializes all registers including the BBSY flag in ICCR2. The other is referred to as an internal reset; this releases the RIIC from the slave-address matched state and initializes the internal counter while retaining other settings.
Page 767: Smbus Operation
RX610 Group 22. I C Bus Interface (RIIC) 22.12 SMBus Operation The RIIC is available for data communication conforming to the SMBus (Version 2.0). To perform SMBus communication, set the SMBS bit in ICMR3 to 1 to select input level conforming to the SMBus for the SCLn pin/SDAn pin function.
Page 768: Packet Error Code (Pec)
RX610 Group 22. I C Bus Interface (RIIC) If the period measured with the TPU or TMR exceeds the total clock low-level extended period [master device] T LOW: : 10 ms (max.) of the SMBus standard or the total of measured periods exceeds the clock low-level detection timeout MEXT : 25 ms (min.) of the SMBus standard, the master device must stop the transaction by issuing a stop condition.
Page 769: Smbus Host Notification Protocol/Notify Arp Master
RX610 Group 22. I C Bus Interface (RIIC) 22.12.3 SMBus Host Notification Protocol/Notify ARP Master In communications over an SMBus, a slave device can temporarily act as a master device to notify the SMBus host (or ARP master) of (or request the SMBus host for) its own slave address or to request its own slave address from the SMBus host.
Page 770: Interrupt Request
RX610 Group 22. I C Bus Interface (RIIC) 22.13 Interrupt Request The RIIC issues four types of interrupt request: transfer error or event generation (arbitration lost, NACK detection, timeout detection, start condition detection, and stop condition detection), receive data full, transmit data empty, and transmit end.
Page 771: Reset States
RX610 Group 22. I C Bus Interface (RIIC) 22.14 Reset States The RIIC has chip reset, RIIC reset, and internal reset functions. Table 22.8 shows the scope of each reset and reset conditions. Table 22.8 Reset Conditions Start Condition/ RIIC Reset Internal Reset Restart Condition Stop Condition...
Page 772: Usage Notes
RX610 Group 22. I C Bus Interface (RIIC) 22.15 Usage Notes 22.15.1 Setting Module Stop Function Module stop state can be entered or canceled using module stop control register B (MSTPCRB). The initial setting is for operation of the RIIC to be halted. RIIC register access is enabled by clearing module stop state. For details of module stop control register B, see section 8, Low Power Consumption.
Page 773: Notes When Communication Is Restarted With The Nack Reception In Master Mode
RX610 Group 22. I C Bus Interface (RIIC) 22.15.5 Notes when Communication is Restarted with the NACK Reception in Master Mode When NACK is received from the slave device in master transmission mode (ICMR3.ACKBR = 1), be sure to end the communication once by issuing the stop condition, and then restart the communication by issuing the start condition.
Page 774: Overview
RX610 Group 23. A/D Converter A/D Converter 23.1 Overview The RX610 Group includes four successive approximation type 10-bit A/D converters (units 0 to 3). Each unit allows up to four analog input channels to be selected. The A/D converter has two kinds of operating modes, that are single mode which converts the analog input of the specified single channel for only once and scan mode which continuously converts the analog inputs of the specified channels up to four.
Page 775 RX610 Group 23. A/D Converter Table 23.2 Comparison of Functions by Each Unit Item Unit 0 (AD0) Unit 1 (AD1) Unit 2 (AD2) Unit 3 (AD3) Analog input channel AN12 AN13 AN10 AN14 AN11 AN15 √ √ √ √ Software Software trigger √...
Page 776 RX610 Group 23. A/D Converter Module data bus Internal data bus AVCC 10-bit VREFH VREFL Control circuit Comparator Sample-and- hold circuit ADI0 interrupt signal Compare-match/input-capture A signal from TPU0 Compare-match/input-capture A signals from TPU0 to TPU5, TPU6 to TPU11 Compare-match A signal from TMR0 Synchronous ADTRG0# circuit...
Page 777 RX610 Group 23. A/D Converter Module data bus Internal data bus AVCC 10-bit VREFH VREFL Control circuit Comparator Sample-and- hold circuit ADI1 interrupt signal Compare-match/input-capture B signal from TPU0 Compare-match/input-capture A signals from TPU0 to TPU5, TPU6 to TPU11 ADTRG1# Compare-match A signal from TMR0 Synchronous circuit...
Page 778 RX610 Group 23. A/D Converter Module data bus Internal data bus AVCC 10-bit VREFH VREFL Control circuit Comparator AN10 Sample-and- hold circuit ADI2 interrupt signal AN11 Compare-match/input-capture signal from TPU0 Compare-match/input-capture A signals from TPU0 to TPU5, TPU6 to TPU11 Compare-match A signal from TMR2 Synchronous ADTRG2#...
Page 779 RX610 Group 23. A/D Converter Module data bus Internal data bus AVCC 10-bit VREFH VREFL AN12 Control circuit AN13 Comparator AN14 Sample-and- hold circuit ADI3 interrupt signal AN15 Compare-match/input-capture D signal from TPU0 Compare-match/input-capture A signals from TPU0 to TPU5, TPU6 to TPU11 ADTRG3# Compare-match A signal from TMR2 Synchronous...
Page 780 RX610 Group 23. A/D Converter Table 23.3 indicates the input pins of the A/D converter Table 23.3 Input Pins of A/D Converter Unit Module Symbol Pin Name Input Function AN0 to AN3 Input Analog input pins ADTRG0# Input External trigger input pin for starting A/D conversion AN4 to AN7 Input Analog input pins...
Page 781: Register Descriptions
RX610 Group 23. A/D Converter 23.2 Register Descriptions Table 23.4 lists the registers of the A/D converter. Table 23.4 Registers of A/D Converter Module Register Value after Access Unit Symbol Register Name Symbol Reset Address Size A/D data register A ADDRA 0000h 0008 8040h...
Page 782: A/D Data Register Y (Addry) (Y = A To D)
RX610 Group 23. A/D Converter 23.2.1 A/D Data Register y (ADDRy) (y = A to D) Addresses: AD0.ADDRA 0008 8040h, AD0.ADDRB 0008 8042h, AD0.ADDRC 0008 8044h, AD0.ADDRD 0008 8046h AD1.ADDRA 0008 8060h, AD1.ADDRB 0008 8062h, AD1.ADDRC 0008 8064h, AD1.ADDRD 0008 8066h AD2.ADDRA 0008 8080h, AD2.ADDRB 0008 8082h, AD2.ADDRC 0008 8084h, AD2.ADDRD 0008 8086h AD3.ADDRA 0008 80A0h, AD3.ADDRB 0008 80A2h, AD3.ADDRC 0008 80A4h, AD3.ADDRD 0008 80A6h ADDPR.DPSEL bit = 0 (Data padded at the LSB end)
Page 783: A/D Control/Status Register (Adcsr)
RX610 Group 23. A/D Converter 23.2.2 A/D Control/Status Register (ADCSR) Addresses: AD0.ADCSR 0008 8050h, AD1.ADCSR 0008 8070h AD2.ADCSR 0008 8090h, AD3.ADCSR 0008 80B0h — ADIE ADST — CH[3:0] Value after reset: [Legend] x: Undefined Symbol Bit Name Description b3 to b0 CH[3:0] Channel Select* Unit...
Page 784 RX610 Group 23. A/D Converter Symbol Bit Name Description ADIE A/D Interrupt Enable 0: ADI interrupt is disabled by completing A/D conversion 1: ADI interrupt is enabled by completing A/D conversion Reserved This bit is always read as an undefined value. The write value should always ...
Page 785: A/D Control Register (Adcr)
RX610 Group 23. A/D Converter 23.2.3 A/D Control Register (ADCR) Addresses: AD0.ADCR 0008 8051h, AD1.ADCR 0008 8071h AD2.ADCR 0008 8091h, AD3.ADCR 0008 80B1h — TRGS[2:0] CKS[1:0] MODE[1:0] Value after reset: Symbol Bit Name Description b1, b0 MODE[1:0] Operation Mode Select b1 b0 0 0: Single mode 0 1: Setting prohibited...
Page 786 RX610 Group 23. A/D Converter Symbol Bit Name Description b7 to b5 TRGS[2:0] Trigger Select Unit Trigger signal Unit 2 b7 b6 b5 0 0 0: Software trigger 0 0 1: Compare-match/input-capture A signals from TPU0 to TPU5 0 1 0: Compare-match A signal from TMR2 0 1 1: Trigger from ADTRG2#* 1 0 0: Compare-match/input-capture C signal from TPU0...
Page 787: Addry Format Select Register (Addpr)
RX610 Group 23. A/D Converter 23.2.4 ADDRy Format Select Register (ADDPR) Addresses: AD0.ADDPR 0008 8052h, AD1.ADDPR 0008 8072h AD2.ADDRR 0008 8092h, AD3.ADDPR 0008 80B2h — — — — — — — DPSEL Value after reset: Symbol Bit Name Description  b6 to b0 Reserved These bits are always read as 0.
Page 788: Operation
RX610 Group 23. A/D Converter 23.3 Operation The RX610 Group includes four units of A/D converter and the each unit has a same feature. Definitions of a single unit are given below. The A/D converter has two operating modes: single mode and scan mode. In single mode, A/D conversion is to be performed for only once on the analog input of the specified single channel.
Page 789 RX610 Group 23. A/D Converter Clear ADCSR.ADST A/D conversion start Channel 0 (AN0) Standby for conversion Channel 1 (AN1) Standby for conversion A/D conversion 1 Standby for conversion A/D conversion 2 Standby for conversion Standby for conversion A/D conversion 3 Channel 2 (AN2) Standby for conversion Channel 3 (AN3)
Page 790: Scan Mode
RX610 Group 23. A/D Converter 23.3.2 Scan Mode In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four. Two types of scan mode are provided, that is, continuous scan mode where A/D conversion is repeatedly performed and single scan mode where A/D conversion is performed for the specified channels for one cycle.
Page 791 RX610 Group 23. A/D Converter Execute A/D conversion repeatedly Clear ADCSR.ADST A/D conversion start A/D conversion time Standby for Channel 0 (AN0) A/D conversion 6 A/D conversion 1 A/D conversion 4 Standby for conversion Standby for conversion conversion Channel 1 (AN1) A/D conversion 2 A/D conversion 5 Standby for conversion...
Page 792: Single Scan Mode
RX610 Group 23. A/D Converter 23.3.2.2 Single Scan Mode In single scan mode, A/D conversion is to be performed for one cycle on the analog inputs of the specified channels as below. When the ADST bit in ADCSR is set to 1 (A/D conversion start) by software, TPU, TMR, or an external trigger input, A/D conversion starts on the first channel in the specified channel group.
Page 793: Input Sampling And A/D Conversion Time
RX610 Group 23. A/D Converter 23.3.3 Input Sampling and A/D Conversion Time The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the conditions of A/D conversion start are generated by software, TPU, TMR, or an external trigger, then starts A/D conversion. Figure 23.8 shows the A/D conversion timing.
Page 794 RX610 Group 23. A/D Converter Table 23.7 A/D Conversion Time Formula Item Symbol A/D conversion start delay time (1) PCLK (MHz) ADCLK (MHz) PCLK (MHz) Setting value of ADSSTR tSPL Input sampling time (2) ADCLK (MHz) Successive conversion time (3) tSAM ADCLK (MHz) A/D conversion time*...
Page 795: Activation By External Triggers
RX610 Group 23. A/D Converter 23.3.4 Activation by External Triggers External trigger signals (ADTRG0# to ADTRG3#) are capable of starting A/D conversion by each of the units. For unit 0, when the setting of the AD0.ADCR.TRGS[2:0] bits is 011b (specifying ADTRG0# as a trigger), a falling edge on the ADTRG0# pin leads to setting of the ADST (A/D conversion start) bit in AD0.ADCR to 1 and thus starts A/D conversion.
Page 796: Activation By The Compare-Match/Input-Capture A To D Signals From Tpu0
RX610 Group 23. A/D Converter 23.3.5 Activation by the Compare-Match/Input-Capture A to D Signals from TPU0 The compare-match/input-capture A to D signals from TPU0 are capable of starting A/D conversion by units 0 to 3. The connections between the units of the converter and the compare-match/input-capture A to D signals from TPU0 are shown in figure 23.10.
Page 797: Activation By The Compare-Match/Input-Capture A Signals From Tpu0 To Tpu5
RX610 Group 23. A/D Converter 23.3.6 Activation by the Compare-Match/Input-Capture A Signals from TPU0 to TPU5 The compare-match/input-capture A signals from TPU0 to TPU5 are capable of starting A/D conversion by units 0 to 3. The compare-match/input-capture A signals from TPU6 to TPU11 are also capable of starting A/D conversion by units 0 to 3.
Page 798: Activation On Compare-Match Of Tmr Units
RX610 Group 23. A/D Converter 23.3.7 Activation on Compare-Match of TMR Units The compare-match A signal from TMR0 is capable of starting A/D conversion by units 0 and 1. In the same way, the compare-match A signal from TMR2 is capable of starting A/D conversion by units 2 and 3. The connections between the units of the converter and the compare-match A signals from TMR0 and TMR2 are shown in figure 23.12.
Page 799: Interrupt Source
RX610 Group 23. A/D Converter 23.4 Interrupt Source The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion while the ADIE bit in ADCSR is set to 1 (after ADI interrupt is enabled by completing A/D conversion). The data transfer controller (DTC) and DMA controller (DMAC) can be activated by an ADI interrupt.
Page 800 RX610 Group 23. A/D Converter Digital output Ideal A/D conversion characteristic Quantization error Analog input voltage 1022 1023 1024 1024 1024 1024 Figure 23.13 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog input voltage Offset error...
Page 801: Usage Notes
RX610 Group 23. A/D Converter 23.6 Usage Notes 23.6.1 Module Stop Function Setting Operation of the A/D converter can be disabled or enabled for each unit using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing the module stop state. For details, see section 8, Low Power Consumption.
Page 802: Permissible Impedance Of Signal Sources
RX610 Group 23. A/D Converter 23.6.5 Permissible Impedance of Signal Sources To realize high-speed conversion 1.0 µs, the A/D conversion accuracy is guaranteed only when the impedance of the signal sources for analog input signals of this LSI circuit is less than or equal to 1.0 kΩ. If a large external capacitance is provided in the case of conversion in single mode, the input load becomes only the actual internal input resistance (6.5 kΩ), so the impedance of the signal source becomes insufficient.
Page 803: Ranges Of Settings For Analog Power Supply And Other Pins
RX610 Group 23. A/D Converter 23.6.7 Ranges of Settings for Analog Power Supply and Other Pins Using this LSI circuit with voltages beyond the ranges given below can have a bad effect on LSI reliability. • Range for the setting of analog input voltages Keep voltages applied to analog input pins (ANn pins) within the range defined by V ≤...
Page 804: Point For Caution Regarding Countermeasures For Noise
RX610 Group 23. A/D Converter 23.6.9 Point for Caution Regarding Countermeasures for Noise To prevent destruction of the circuits for the analog input pins by abnormal voltages such as excessively large surges, connect capacitors as shown in figure 23.17 between AVcc and AVss, and between V and V ;...
Page 805: Realizing High-Speed Conversion
RX610 Group 23. A/D Converter 23.6.10 Realizing High-Speed Conversion To realize high-speed conversion, connect external 0.1-μF capacitors between the analog input pins (AN0 to AN15) and . This is shown in figure 23.18. However, to prevent the impedance of the signal source due to the input capacitance REFL of the sample-and-hold circuit of the A/D converter from affecting the conversion time, the externally connected capacitors must be fully charged before the start of conversion.
Page 806: Notes When Using Multiple Units Of A/D Converter
RX610 Group 23. A/D Converter 23.6.11 Notes when Using Multiple Units of A/D Converter Since the same power supply is used between the units of the A/D converter contained in the RX610 Group, when multiple units are used and conversion start timing between each unit is different, conversion accuracy may get affected. When the conversion accuracy is affected, adopt the following methods and perform an adequate evaluation.
Page 807 RX610 Group 23. A/D Converter (2) Register settings of recommended operation The following registers and bits should be set to the same value between all of the units. • A/D sampling state register (ADSSTR) • Clock select bits (ADCR.CKS[1:0]) • Trigger select bits (ADCR.TRGS[2:0]) (3) Trigger selection corresponding to number of units The number of units that can be activated depends on the selected trigger.
Page 808: Overview
RX610 Group 24. D/A Converter D/A Converter 24.1 Overview The RX610 Group includes a two-channel of 10-bit D/A converter. Table 24.1 lists the specifications of the D/A converter and figure 24.1 shows a block diagram of the D/A converter. Table 24.1 Specifications of D/A Converter Item Specifications...
Page 809 RX610 Group 24. D/A Converter Table 24.2 lists the pin configuration of the D/A converter. Table 24.2 Pin Configuration of D/A Converter Pin Name Function Input Analog circuit power supply pin Input Analog circuit ground pin VREFH Input D/A converter reference power supply pin VREFL Input D/A converter reference ground pin...
Page 810: Register Descriptions
RX610 Group 24. D/A Converter 24.2 Register Descriptions Table 24.3 lists the registers of the D/A converter. Table 24.3 Registers of D/A Converter Register Name Symbol Value after Reset Address Access Size D/A data register 0 DADR0 0000h 0008 80C0h D/A data register 1 DADR1 0000h...
Page 811: D/A Control Register (Dacr)
RX610 Group 24. D/A Converter 24.2.2 D/A Control Register (DACR) Address: 0008 80C4h DAOE1 DAOE0 Value after reset: Symbol Bit Name Description  b4 to b0 Reserved These bits are read as 1. The write value should always be 1. DAE* D/A Enable 0: D/A conversion is independently controlled on...
Page 812 RX610 Group 24. D/A Converter DAE Bit (D/A Enable) The DAE bit controls D/A conversion in combination with the DAOE0 and DAOE1 bits. When the DAE bit is 0, D/A conversion is independently controlled on channels 0 and 1. When the DAE bit is 1, D/A conversion on channels 0 and 1 is controlled as a single whole.
Page 813: Dadry Format Select Register (Dadpr)
RX610 Group 24. D/A Converter 24.2.3 DADRy Format Select Register (DADPR) Address: 0008 80C5h DPSEL Value after reset: Symbol Bit Name Description b6 to b0  Reserved These bits are always read as 0. The write value should always be 0. DPSEL DADRy Format Select 0: D/A data register is padded at the LSB end.
Page 814: Operation
RX610 Group 24. D/A Converter 24.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When the DAOEn bit (n = 0, 1) in DACR is set to 1, D/A converter is enabled and the conversion result is output. An operation example of D/A conversion on channel 0 is shown below.
Page 815: Usage Notes
RX610 Group 24. D/A Converter 24.4 Usage Notes 24.4.1 Module Stop Function Setting Operation of the D/A converter can be disabled or enabled by using the module stop control register. The initial setting is for operation of the D/A converter to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 8, Low Power Consumption.
Page 816 RX610 Group 24. D/A Converter Further, when multiple units of A/D converter are operated, implement the method described in section 23.6.11, Notes when Using Multiple Units of A/D Converter, and match one conversion period between each of the units. Figure 24.3 shows an example of procedure of rewriting the DADR register from 000h to 3FFh. •...
Page 817: Overview
RX610 Group 25. RAM The RX610 Group has a high-speed static RAM. 25.1 Overview Table 25.1 lists the specifications of the RAM. Table 25.1 Specifications of the RAM Item Description RAM capacity 128 Kbytes (RAM0: 64 Kbytes, RAM1: 64 Kbytes) RAM address RAM0: 0000 0000h to 0000 FFFFh RAM1: 0001 0000h to 0001 FFFFh...
Page 818: Overview
RX610 Group 26. ROM (Flash Memory for Code Storage) ROM (Flash Memory for Code Storage) The RX610 has two flash-memory modules: a maximum 2-Mbyte ROM for storing code and a 32-Kbyte data flash block for storing data. This section covers the flash memory for code storage. For the data flash, see section 27, Data Flash (Flash Memory for Data Storage).
Page 819 RX610 Group 26. ROM (Flash Memory for Code Storage) Notes: 1. Each product has different ROM sizes. Product Code ROM Size ROM Addresses R5F56108 2 Mbytes FFE0 0000h to FFFF FFFFh R5F56107 1.5 Mbytes FFE8 0000h to FFFF FFFFh R5F56106 1 Mbyte FFF0 0000h to FFFF FFFFh R5F56104...
Page 820 RX610 Group 26. ROM (Flash Memory for Code Storage) Mode pins Mode decoder Memory interface ROM mat FMODR User mat: Up to 2 Mbytes FASTAT User boot mat: 16 Kbytes FAEINT DFLRE DFLWE FCURAME FCU RAM FSTATR0 FIFERR FSTATR1 FENTRYR FRDYI FRESETR FCU firmware store area: 8 Kbytes...
Page 821: Register Descriptions
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2 Register Descriptions Table 26.3 lists the registers related to ROM. Although some registers have bits related to data flash, this section deals only with the bits related to ROM. For details on the bits related to the data flash, see section 27.2, Register Descriptions in the data flash section.
Page 822: Flash Mode Register (Fmodr)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.1 Flash Mode Register (FMODR) Address: 007F C402h — — — — — — — FRDMD Value after reset: Symbol Bit Name Description  b3 to b0 Reserved These bits are always read as 0. The write value should always be 0. FRDMD FCU Read Mode Select 0: Memory Area Read Method...
Page 823: Flash Access Status Register (Fastat)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.2 Flash Access Status Register (FASTAT) Address: 007F C410h — — — ROMAE CMDLK DFLAE DFLRPE DFLWPE Value after reset: Symbol Bit Name Description DFLWPE Data Flash Programming/Erasure See section 27, Data Flash (Flash Memory for Data R/(W)* Protection Violation Storage).
Page 824 RX610 Group 26. ROM (Flash Memory for Code Storage) ROMAE Bit (ROM Access Violation) This bit indicates whether a ROM access violation occurred. When the ROMAE bit is set to 1, the ILGLERR bit in FSTATR0 is set to 1, placing the FCU in the command-locked state.
Page 825: Flash Access Error Interrupt Enable Register (Faeint)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.3 Flash Access Error Interrupt Enable Register (FAEINT) Address: 007F C411h ROMAEIE CMDLKIE DFLAEIE DFLRPEIE DFLWPEIE Value after reset: Symbol Bit Name Description DFLWPEIE Data Flash Programming/Erasure See section 27, Data Flash (Flash Memory for Data Protection Violation Interrupt Enable Storage).
Page 826: Fcu Ram Enable Register (Fcurame)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.4 FCU RAM Enable Register (FCURAME) Address: 007F C454h KEY[7:0] Value after reset: — — — — — — — FCRME Value after reset: Symbol Bit Name Description FCRME FCU RAM Enable 0: Access to the FCU RAM disabled 1: Access to the FCU RAM enabled ...
Page 827: Flash Status Register 0 (Fstatr0)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.5 Flash Status Register 0 (FSTATR0) Address: 007F FFB0h — FRDY ILGLERR ERSERR PRGERR SUSRDY ERSSPD PRGSPD Value after reset: Symbol Bit Name Description PRGSPD Programming Suspend Status 0: Other than the status described below 1: During programming suspend processing or programming suspended ERSSPD...
Page 828 RX610 Group 26. ROM (Flash Memory for Code Storage) ERSSPD Bit (Erasure Suspend Status) This bit is used to indicate that the FCU enters the erasure suspend processing state or erasure suspended state (see section 26.7, Suspending Operation). [Setting condition] •...
Page 829 RX610 Group 26. ROM (Flash Memory for Code Storage) ILGLERR Bit (Illegal Command Error) This bit is used to indicate that the FCU detects any illegal command or ROM/data flash access. When the ILGLERR bit is set to 1, the FCU is placed in the command-locked state (see section 26.8.2, Error Protection). [Setting conditions] •...
Page 830: Flash Status Register 1 (Fstatr1)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.6 Flash Status Register 1 (FSTATR1) Address: 007F FFB1h — — — — — — FCUERR FLOCKST Value after reset: x: Undefined Symbol Bit Name Description  b1, b0 Reserved The read value is undefined and these bits cannot be modified. ...
Page 831: Flash Ready Interrupt Enable Register (Frdyie)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.7 Flash Ready Interrupt Enable Register (FRDYIE) Address: 007F C412h — — — — — — — FRDYIE Value after reset: Symbol Bit Name Description FRDYIE Flash Ready Interrupt Enable 0: FRDYI interrupt requests disabled 1: FRDYI interrupt requests enabled ...
Page 832: Flash P/E Mode Entry Register (Fentryr)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.8 Flash P/E Mode Entry Register (FENTRYR) Address: 007F FFB2h FEKEY[7:0] Value after reset: — — — — — FENTRYD FENTRY1 FENTRY0 Value after reset: Symbol Bit Name Description FENTRY0 ROM P/E Mode Entry 0 0: ROM within 1 Mbyte* is in ROM read mode 1: ROM within 1 Mbyte*...
Page 833 RX610 Group 26. ROM (Flash Memory for Code Storage) FENTRY0 Bit (ROM P/E Mode Entry 0) This bit is used to place 1 Mbyte of ROM (read addresses: FFF0 0000h to FFFF FFFFh, programming/erasure addresses 00F0 0000h to 00FF FFFFh) in P/E mode. [Writing-enable conditions (when all of the following conditions are met)] •...
Page 834 RX610 Group 26. ROM (Flash Memory for Code Storage) FEKEY[7:0] Bits (Key Code) These bits enable or disable rewriting of the FENTRYD, FENTRY1*, and FENTRY0 bits. Data written to the FEKEY[7:0] bits is not retained. Note: * Cannot be used in a product whose ROM size is equal to or smaller than 1 Mbyte. Table 26.4 Correspondence of FENTRY1 and FENTRY0 Bits in Each Product FENTRY1...
Page 835: Flash Protection Register (Fprotr)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.9 Flash Protection Register (FPROTR) Address: 007F FFB4h FPKEY[7:0] Value after reset: — — — — — — — FPROTCN Value after reset: Symbol Bit Name Description FPROTCN Lock Bit Protection Cancel 0: Protection with a lock bit enabled 1: Protection with a lock bit disabled ...
Page 836: Flash Reset Register (Fresetr)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.10 Flash Reset Register (FRESETR) Address: 007F FFB6h FRKEY[7:0] Value after reset: — — — — — — — FRESET Value after reset: Symbol Bit Name Description FRESET Flash Reset 0: FCU is not reset 1: FCU is reset ...
Page 837: Fcu Command Register (Fcmdr)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.11 FCU Command Register (FCMDR) Address: 007F FFBAh CMDR[7:0] Value after reset: PCMDR[7:0] Value after reset: Symbol Bit Name Description b7 to b0 PCMDR[7:0] Precommand Store the command immediately before the last command received by the FCU.
Page 838: Fcu Processing Switching Register (Fcpsr)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.12 FCU Processing Switching Register (FCPSR) Address: 007F FFC8h — — — — — — — — Value after reset: — — — — — — — ESUSPMD Value after reset: Symbol Bit Name Description...
Page 839: Flash P/E Status Register (Fpestat)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.13 Flash P/E Status Register (FPESTAT) Address: 007F FFCCh — — — — — — — — Value after reset: PEERRST[7:0] Value after reset: Symbol Bit Name Description b7 to b0 PEERRST[7:0] P/E Error Status 01h: Programming error against areas protected by a lock bit...
Page 840: Peripheral Clock Notification Register (Pckar)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.14 Peripheral Clock Notification Register (PCKAR) Address: 007F FFE8h — — — — — — — — Value after reset: PCKA[7:0] Value after reset: Symbol Bit Name Description b7 to b0 PCKA[7:0] Peripheral Clock Notification These bits are used to set the peripheral clock (PCLK) at the programming/erasure for the ROM/data flash.
Page 841: Flash Write Erase Protection Register (Fwepror)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.2.15 Flash Write Erase Protection Register (FWEPROR) Address: 0008 C289h — — — — — — FLWE[1:0] Value after reset: Symbol Bit Name Description b1, b0 FLWE[1:0] Flash Write/Erase b1 and b0 0 0: Write/erase disabled 0 1: Write/erase enabled 1 0: Write/erase disabled (initial value)
Page 842: Configuration Of Memory Mats For The Rom
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.3 Configuration of Memory Mats for the ROM The ROM of products in the RX610 Group is configured of a maximum 2-Mbyte user mat and a 16-Kbyte user boot mat. The address ranges occupied by these mats are shown in figure 26.2. Note that for the user mat, the address range for reading differs from the address range for programming and erasure.
Page 843: Operating Modes Associated With The Rom
RX610 Group 26. ROM (Flash Memory for Code Storage) User mat Erasure block Address FFE0 0000h EB27 128 Kbytes × 11 blocks EB17 Address FFF5 FFFFh Address FFF6 0000h EB16 64 Kbytes × 9 blocks EB08 Address FFFE FFFFh EB07 Address FFFF 0000h 8 Kbytes ×...
Page 844 RX610 Group 26. ROM (Flash Memory for Code Storage) Reset state RES# = 0 RES# = 0 RES# = 0 RES# = 0 RES# = 1 RES# = 1 RES# = 1 MD1 = 0 MD1 = 1 MD1 = 1 MD0 = 1 MD0 = 0 MD0 = 1...
Page 845 RX610 Group 26. ROM (Flash Memory for Code Storage) Reading, programming, and erasing of the ROM in an on-board device can proceed if the device is in boot, user-boot, or single-chip mode (with on-chip ROM enabled), or in on-chip-ROM-enabled expansion mode. Which mats are programmable and erasable, the mat from which booting up proceeds after a reset, etc., differs with the mode.
Page 846: Programming And Erasing The Rom
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.6 Programming and Erasing the ROM The ROM is programmed and erased by issuing commands to a dedicated sequencer (FCU) for programming and erasure. The FCU has five modes. For programming and erasure, the mode is changed and then commands for programming and erasure are issued.
Page 847: Rom Read Modes
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.6.1.1 ROM Read Modes The ROM read modes are for high-speed reading of the ROM. Access to an address for reading can be accomplished in one cycle of ICLK. ROM/data-flash read mode and data-flash P/E mode are the two kinds of ROM reading mode. (1) ROM/Data Flash Read Mode This mode is for reading the ROM and data-flash memory.
Page 848: Fcu Commands
RX610 Group 26. ROM (Flash Memory for Code Storage) Note: * Cannot be used in a product whose ROM size is equal to or smaller than 1 Mbyte. (3) ROM Lock-Bit Read Mode The ROM lock-bit read mode is for reading the values of the lock bits of the ROM. The FCU enters this mode when a lock-bit read mode transition command is received in ROM P/E modes.
Page 849 RX610 Group 26. ROM (Flash Memory for Code Storage) Table 26.8 FCU Command Formats First Second Third 4th to 5th 7th to 130th 131st Cycle Cycle Cycle Cycles Cycle Cycles Cycle Command         ...
Page 850: Connections Between Fcu Modes And Commands
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.6.3 Connections between FCU Modes and Commands The sets of FCU commands that can be accepted in each of the FCU modes are fixed. Furthermore, which commands are acceptable in a given FCU mode also depends on the state of the FCU. Issuing of an FCU command must follow checking of the FCU's state after transitions of the FCU mode.
Page 851: Fcu Command Usage
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.6.4 FCU Command Usage The set of FCU commands consists of commands for FCU mode transitions, actually programming or erasing the ROM, error processing, and suspension and resumption. The following passages describe the various commands. For a description of the modes and states where the respective commands are acceptable, see section 26.6.3, Connections between FCU Modes and Commands.
Page 852 RX610 Group 26. ROM (Flash Memory for Code Storage) Start FRDY bit check "1" "0" Timeout ILGLERR, ERSERR, or PRGERR = 1 Error check (tE128K)* ILGLERR bit initialization check "1" "0" FRESETR.FRESET = 1 Read FASTAT writing ILGLERR = 0 ERSERR = 0 PRGERR = 0 Wait...
Page 853 RX610 Group 26. ROM (Flash Memory for Code Storage) (3) Switching to ROM P/E Normal Mode Two methods are available for the transition to ROM P/E normal mode: setting the FENTRYR register while the FCU is in ROM read mode (see section 26.6.1, FCU Modes), or issuing the normal mode transition command while the FCU is in ROM P/E mode (see figure 26.8).
Page 854 RX610 Group 26. ROM (Flash Memory for Code Storage) (5) Switching to ROM Lock-Bit Read Mode Clearing the FRDMD bit in FMODR (memory area method) issues a lock bit read mode transition (lock bit read 1) command. After the transition to ROM lock bit read mode, lock bit value are obtained by read access to the area for ROM programming and erasure.
Page 855: Programming And Erasure Procedures
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.6.4.2 Programming and Erasure Procedures The following passages describe the flow of procedures for programming or erasing the ROM. For details on the acceptance of commands by the FCU, see section 26.6.3, Connections between FCU Modes and Commands. Figure 26.11 is a simple flowchart of the procedure for executing FCU commands.
Page 856 RX610 Group 26. ROM (Flash Memory for Code Storage) (1) Transferring Firmware to the FCU RAM FCU commands can only be used if the FCU RAM holds the firmware for the FCU. The FCU RAM does not hold the FCU firmware immediately after the chip has been booted up, so the firmware must be copied from the FCU firmware area to the FCU RAM.
Page 857 RX610 Group 26. ROM (Flash Memory for Code Storage) (4) Using the Peripheral Clock Notification Command The peripheral clock is used in programming and erasing the ROM, so the frequency of this clock has to be set in the PCKAR. Frequencies in the range from 8 to 50 MHz are selectable. Do not set frequencies out of this range. The peripheral clock notification command is used after the PCKAR setting has been made.
Page 858 RX610 Group 26. ROM (Flash Memory for Code Storage) Start Set PCKAR to frequency of peripheral clock (PCLK) Write E9h to ROM programming/erasure address in byte access Write 03h to ROM programming/erasure address in byte access n = 1 Write 0F0Fh data to ROM programming/erasure address in n = n + 1 word access...
Page 859 RX610 Group 26. ROM (Flash Memory for Code Storage) (5) Programming The programming command is used to write data to the ROM. In the first and second cycles for the peripheral clock notification command, respectively, the values E8h and 80h are written to the address range for programming and erasure of the ROM.
Page 860 RX610 Group 26. ROM (Flash Memory for Code Storage) Start Write E8h to ROM programming/ erasure address in byte access Write 80h to ROM programming/ erasure address in byte access Write programming data to start address of programming destination in word access n = 1 Write programming data to ROM...
Page 861 RX610 Group 26. ROM (Flash Memory for Code Storage) (6) Erasure To erase data from the ROM, use the block erase command. Write 20h to the ROM programming/erasure address in byte access in the first cycle of the block erase command. When D0h is written to an arbitrary address in an erasure target block in byte access in the second cycle, the FCU start the erasure processing for the ROM.
Page 862 RX610 Group 26. ROM (Flash Memory for Code Storage) (7) Writing to/Erasing Lock Bit Each erasure block in the user mat includes a lock bit. To write to a lock bit, use the lock bit programming command. In the first cycle of the lock bit programming command, 77h is programmed to the ROM programming/erasure address in byte access.
Page 863 RX610 Group 26. ROM (Flash Memory for Code Storage) (8) Reading Lock Bits Lock bits can be read out by either reading from a memory area or reading from a register. The lock bit read 2 command is issued in the case of the register-reading method (i.e. when the FRDMD bit in FMODR is 1).
Page 864: Error Processing
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.6.4.3 Error Processing The following passages describe the flow of error processing. For details on errors, see section 26.8, Protection. (1) Checking Flash Status Register 0 (FSTATR0) To check FSTATR0, read FSTATR0 directly or read the ROM programming/erasure address in ROM status read mode. For the reading in ROM status read mode, see section 26.6.4.1 (4)Switching to ROM Status Read Mode.
Page 865: Suspension And Resumption
RX610 Group 26. ROM (Flash Memory for Code Storage) (3) Initializing the FPU When a timeout leads to the FRDY bit in FSTATR0 not being set to 1 after an FCU command has been issued, FRESETR must be used to initialize the FCU. This is also necessary when the FCUERR bit in FSTATR1 has been set. In either case, maintain the FRESET bit in FRESETR at logical one over a period of at least tRESW2 (see section 28, Electrical Characteristics).
Page 866 RX610 Group 26. ROM (Flash Memory for Code Storage) Start LGLERR, ERSERR, PRGERR, FCUERR = 1 Error bit check ILGLERR = 0 ERSERR = 0 PRGERR = 0 FCUERR = 0 "0" SUSRDY bit check FCUERR = 0 FCUERR bit check "1"...
Page 867 RX610 Group 26. ROM (Flash Memory for Code Storage) (2) Resuming Programming or Erasure To resume a suspended programming/erasure processing, use the P/E resume command. When the settings of FENTRYR are changed during suspension, reset FENTRYR to the value immediately before a P/E suspend command is issued, and then issue a P/E resume command.
Page 868: Suspending Operation
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.7 Suspending Operation The ROM cannot be read out during programming/erasure. The ROM can be read out by suspending the ROM programming/erasure with the P/E suspend command. The P/E suspend command includes one programming mode and two erasure modes (suspension priority mode and erasure priority mode).
Page 869: Suspension During Erasure (Suspension Priority Mode)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.7.2 Suspension during Erasure (Suspension Priority Mode) Figure 26.22 shows the suspend operation of erasure when the erasure suspend mode is set to the suspension priority mode (ESUSPMD bit in FCPSR is 0). When receiving an erasure-related command, the FCU clears the FSTATR0.FRDY bit to 0 to start erasure.
Page 870: Suspension During Erasure (Erasure Priority Mode)
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.7.3 Suspension during Erasure (Erasure Priority Mode) Figure 26.23 shows the suspend operation of erasure when the erasure suspend mode is set to the erasure priority mode (ESUSPMD bit in FCPSR is 1). The control method of erasure pulses in erasure priority mode is the same as that of programming pulses for the programming suspend processing.
Page 871: Protection
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.8 Protection Protection against programming/erasure for the ROM includes software protection and error protection. 26.8.1 Software Protection With the software protection, the ROM programming/erasure is prohibited by the settings of the control register or user mat lock bit.
Page 872 RX610 Group 26. ROM (Flash Memory for Code Storage) Table 26.10 Error Protection Types (Types Dedicated to ROM and Types Common to ROM and Data Flash) Type Description FENTRYR setting More than one bit is set to 1 among the FENTRYD, FENTRY1*, and error FENTRY0 bits in FENTRYR The FENTRYR setting at suspension disagrees with that at resume...
Page 873: User Boot Mode
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.9 User Boot Mode When the reset clearing is executed with the MD1 and MD0 pins set to user boot mode, the FCU enters user boot mode. The reset vector at this time is address FF7F FFFCh in the user boot mat. For other vector tables, see the normal vector table (see section 10, Interrupt Control Unit (ICU)).
Page 874: Id Code Protection
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.10.2 ID Code Protection This function is used to prohibit reading/programming/erasure from the host. Using the control code and ID code written in the ROM, ID code protection is enabled or disabled and ID code protection is judged.
Page 875 RX610 Group 26. ROM (Flash Memory for Code Storage) Table 26.11 Specifications for ID Code Protection Control Code ID Code State of Protection Operations at the Time of SCI Connection As desired Protection enabled Matching ID code: ID code protection is lifted, and this is (authentication method 1) followed by a transition to the state of waiting for a host command.
Page 876: State Transitions In Boot Mode
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.10.3 State Transitions in Boot Mode Figure 26.26 is a diagram of the state transitions in boot mode. 00h,..,00h (Bit rate adjustment) Activated in boot mode Bit rate adjustment (Reset in boot mode) Inquiry command Wait for inquiry/ Execute inquiry/...
Page 877 RX610 Group 26. ROM (Flash Memory for Code Storage) (1) Matching the Bit Rates When the RX610 is activated in boot mode, the bit rate of the SCI is automatically adjusted to match that of the host. On completion of this adjustment, the RX610 transmits the value 00h to the host. On subsequent correct reception of the value 55h sent from the host, the RX610 enters the state of waiting for a host command for inquiry or selection.
Page 878: Automatic Adjustment Of The Bit Rate
RX610 Group 26. ROM (Flash Memory for Code Storage) commands, explicit execution of erasure is not necessary unless newly programmed data are to be erased without a further reset. Other than the programming and erasure commands, commands from the host for execution in this state include those for sum checking of the user mat and user boot mat, blank checking (to confirm erasure), reading from memory, and acquiring state information.
Page 879: Inquiry/Selection Host Command Wait State
RX610 Group 26. ROM (Flash Memory for Code Storage) Table 26.12 Conditions for Automatic Bit-Rate Adjustment to be Possible Bit Rate of the SCI in the Host Range of Frequency for the EXTAL Signal 9,600 bps 8 to 14 MHz 19,200 bps 8 to 14 MHz 26.10.5...
Page 880 RX610 Group 26. ROM (Flash Memory for Code Storage) Start Supported device inquiry Device selection Clock mode inquiry Clock mode selection Multiplication ratio inquiry Operating frequency inquiry New bit rate selection User boot mat information inquiry Inquiry regarding mat programming User mat information inquiry information Erasure block information inquiry...
Page 881 RX610 Group 26. ROM (Flash Memory for Code Storage) (1) Supported Device Inquiry In response to a supported device inquiry command sent from the host, the RX610 returns the information concerning the devices supported by the embedded program for boot mode. If the supported device inquiry command comes after the host has selected a device, the RX610 only returns the information concerning the selected device.
Page 882 RX610 Group 26. ROM (Flash Memory for Code Storage) (2) Device Selection In response to a device selection command sent from the host, the RX610 checks if the selected device is supported. When the selected device is supported, the RX610 specifies this device as the device for use and returns a response (06h). If the selected device is not supported or the sent command is illegal, the RX610 returns an error response (90h).
Page 883 RX610 Group 26. ROM (Flash Memory for Code Storage) (4) Clock Mode Selection In response to a clock mode selection command sent from the host, the RX610 checks if the selected clock mode is supported. When the selected mode is supported, the RX610 specifies this clock mode for use and returns a response (06h).
Page 884 RX610 Group 26. ROM (Flash Memory for Code Storage) (5) Multiplication Ratio Inquiry In response to a multiplication ratio inquiry command sent from the host, the RX610 returns the clock types, the number of multiplication/division ratios, and the multiplication division ratios supported. Command Response Size...
Page 885 RX610 Group 26. ROM (Flash Memory for Code Storage) (6) Operating Clock Frequency Inquiry In response to an operating clock frequency inquiry command sent from the host, the RX610 returns the minimum and maximum frequencies for each clock. Command Response Size Clock type count...
Page 886 RX610 Group 26. ROM (Flash Memory for Code Storage) (7) User Boot Mat Information Inquiry In response to a user boot mat information inquiry command sent from the host, the RX610 returns the number of user boot mat areas and their addresses. Command Response Size...
Page 887 RX610 Group 26. ROM (Flash Memory for Code Storage) (8) User Mat Information Inquiry In response to a user mat information inquiry command sent from the host, the RX610 returns the number of user mat areas and their addresses. Command Response Size Area count...
Page 888 RX610 Group 26. ROM (Flash Memory for Code Storage) (9) Erasure Block Information Inquiry In response to an erasure block information inquiry command sent from the host, the RX610 returns the number of erasure blocks in the user mat and their addresses. Command Response Size...
Page 889 RX610 Group 26. ROM (Flash Memory for Code Storage) (11) New Bit Rate Selection In response to a new bit rate selection command sent from the host, the RX610 checks if the on-chip SCI can be set to the selected new bit rate. When the SCI can be set to the new bit rate, the RX610 returns a response (06h) and sets the SCI to the new bit rate.
Page 890 RX610 Group 26. ROM (Flash Memory for Code Storage) [Legend] Size (1 byte): Total number of bytes in the bit rate, input frequency, clock type count, and multiplication ratio fields Bit rate (2 bytes): New bit rate (for example, 00C0h indicates 19200 bps) 1/100 of the new bit rate value should be specified.
Page 891 RX610 Group 26. ROM (Flash Memory for Code Storage) • Multiplication ratio error A multiplication ratio error occurs when the multiplication ratio specified through a new bit rate selection command does not match the clock mode selected through a clock mode selection command. To check the selectable multiplication ratios, issue a multiplication ratio inquiry command.
Page 892 RX610 Group 26. ROM (Flash Memory for Code Storage) (13) Embedded Program Status Inquiry In response to an embedded program status inquiry command sent from the host, the RX610 returns its current status. The embedded program status inquiry command can be issued in both the inquiry/selection host command wait state and programming/erasure host command wait state.
Page 893: Id Code Wait State
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.10.6 ID Code Wait State Table 26.16 shows the host command available in the ID code wait state. Table 26.16 ID Code Check Host Command Host Command Name Function ID code check Performs the ID code check If the host has sent an undefined command, the RX610 returns a response indicating a command error.
Page 894: Programming/Erasure Host Command Wait State
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.10.7 Programming/Erasure Host Command Wait State Table 26.17 shows the host commands available in the programming/erasure host command wait state. Table 26.17 Programming/Erasure Host Commands Host Command Name Function User boot mat programming selection Selects the program for user boot mat programming User mat programming selection Selects the program for user mat programming...
Page 895 RX610 Group 26. ROM (Flash Memory for Code Storage) Start User boot mat programming selection Programming selection User mat programming selection 256-byte programming Address and data specification Address and data specification 256-byte programming 256-byte programming Address FFFF FFFFh specification Figure 26.31 Procedure for ROM Programming in Boot Mode Start Erasure selection...
Page 896 RX610 Group 26. ROM (Flash Memory for Code Storage) Command Response (2) User Mat Programming Selection In response to a user mat programming selection command sent from the host, the RX610 selects the program for user mat programming and waits for programming data. Command Response (3) 256-Byte Programming...
Page 897 RX610 Group 26. ROM (Flash Memory for Code Storage) (4) Erasure Selection In response to an erasure selection command sent from the host, the RX610 selects the erasure program and waits for erasure block specification. Command Response (5) Block Erasure In response to a block erasure command sent from the host, the RX610 erases the ROM.
Page 898 RX610 Group 26. ROM (Flash Memory for Code Storage) (6) Memory Read In response to a memory read command sent from the host, the RX610 reads data from the ROM. After completing ROM reading successfully, the RX610 returns the data stored in the address specified by the memory read command. If the RX610 has failed to read the ROM, the RX610 returns an error response (D2h).
Page 899 RX610 Group 26. ROM (Flash Memory for Code Storage) (7) User Boot Mat Checksum In response to a user boot mat checksum command sent from the host, the RX610 sums the user boot mat data in byte units and returns the result (checksum). Command Response Size...
Page 900 RX610 Group 26. ROM (Flash Memory for Code Storage) (10) User Mat Blank Check In response to a user mat blank check command sent from the host, the RX610 checks whether the user mat is completely erased. When the user mat is completely erased, the RX610 returns a response (06h). If the user mat has an unerased area, the RX610 returns an error response (sends CDh and 52h in that order).
Page 901 RX610 Group 26. ROM (Flash Memory for Code Storage) (12) Lock Bit Program In response to a lock bit program command sent from the host, the RX610 writes to a lock bit and locks the specified block. After completing the lock bit blocking successfully, the RX610 returns a response (06h). If the RX610 has failed to lock, the RX610 returns an error response (F7h).
Page 902 RX610 Group 26. ROM (Flash Memory for Code Storage) (14) Lock Bit Disable In response to a lock bit disable command sent from the host, the RX610 disables a lock bit. Command Response (15) Embedded Program Status Inquiry For details, refer to section 26.10.5, Inquiry/Selection Host Command Wait State. R01UH0032EJ0120 Rev.1.20 Page 902 of 1006 Feb 20, 2013...
Page 903: Id Code Protection On Connection Of The On-Chip Debugger
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.11 ID Code Protection on Connection of the On-Chip Debugger This function is used to prohibit connection with the on-chip debugger. When connecting an on-chip debugger, the control code and ID code that have been written to the ROM are used to determine whether ID code protection on connection of the on-chip debugger is enabled or disabled and to judge ID code protection on connection of the on-chip debugger.
Page 904: Rom Code Protection
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.12 ROM Code Protection ROM code protection is a facility for prohibiting a PROM programmer from reading from or writing to flash memory. The ROM code in flash memory is a 32-bit code. Figure 26.33 shows the configuration of ROM codes. Set ROM codes as 32-bit units.
Page 905: Usage Notes
RX610 Group 26. ROM (Flash Memory for Code Storage) 26.13 Usage Notes (1) Areas where Programming or Erasure is Suspended Data in areas where programming or erasure is suspended are undefined. To avoid malfunctions due to the reading of undefined data, prevent the reading of data and execution of code from areas where programming or erasure is currently suspended.
Page 906 RX610 Group 26. ROM (Flash Memory for Code Storage) (8) Actions Prohibited during Programming and Erasure The following prohibitions must be observed to prevent damage to the flash memory during programming or erasure. • Do not allow the power-supply voltage of RX610 to go outside the specified range for operation. •...
Page 907: Overview
RX610 Group 27. Data Flash (Flash Memory for Data Storage) Data Flash (Flash Memory for Data Storage) The RX610 has a maximum 2-Mbyte flash memory for storing program code (ROM) and a 32-Kbyte flash memory for storing data (data flash). This section covers the flash memory for data storage.
Page 908 RX610 Group 27. Data Flash (Flash Memory for Data Storage) Mode pins Mode decoder Memory interface ROM mat unit FMODR User mat: Up to 2 Mbytes FASTAT User boot mat: 16 Kbytes FAEINT DFLRE DFLWE FCURAME FCU RAM FSTATR0 FIFERR FSTATR1 FENTRYR FRDYI...
Page 909: Register Descriptions
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2 Register Descriptions Table 27.3 lists the registers related to the data flash memory. Some registers also have bits related to the ROM, but this section deals only with the bits that are relevant to the data flash. For registers containing bits with common functions for the ROM and data flash (FRDYIE, FCURAME, FSTATR0, FSTATR1, FRESETR, FCMDR, FCPSR, PCKAR, and FWEPROR) and details on the functions of bits dedicated to the ROM, see section 26.2, Register Descriptions.
Page 910: Flash Mode Register (Fmodr)
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2.1 Flash Mode Register (FMODR) Address: 007F C402h — — — — — — — FRDMD Value after reset: Symbol Bit Name Description  b3 to b0 Reserved These bits are always read as 0. The write value should always be 0. FRDMD FCU Read Mode Select 0: Memory Area Reading Method...
Page 911: Flash Access Status Register (Fastat)
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2.2 Flash Access Status Register (FASTAT) Address: 007F C410h — — — ROMAE CMDLK DFLAE DFLRPE DFLWPE Value after reset: Symbol Bit Name Description DFLWPE Data Flash 0: No data flash programming/erasure command is issued R/(W)* Programming/Erasure Protection which conflicts with the DFLWE settings...
Page 912 RX610 Group 27. Data Flash (Flash Memory for Data Storage) EEPWPE Bit (Data Flash Programming/Erasure Protection Violation) This bit is used to indicate whether or not the programming/erasure protection set by DFLWE is violated. [Setting condition] • A programming/erasure command is issued for a data flash area for which programming or erasure is disabled by DFLWE.
Page 913: Flash Access Error Interrupt Enable Register (Faeint)
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2.3 Flash Access Error Interrupt Enable Register (FAEINT) Address: 007F C411h — — — ROMAEIE CMDLKIE DFLAEIE DFLRPEIE DFLWPEIE Value after reset: Symbol Bit Name Description DFLWPEIE Data Flash Programming/Erasure 0: FIFERR interrupt requests disabled when the DFLWPE Protection Violation Interrupt Enable bit in FASTAT is set to 1...
Page 914 RX610 Group 27. Data Flash (Flash Memory for Data Storage) DFLAEIE Bit (Data Flash Read Protection Violation Interrupt Enable) This bit is used to enable or disable FIFERR interrupt requests when a data flash access violation occurs and the DFLAE bit in FASTAT is set to 1.
Page 915: Data Flash Read Enable Register (Dflre)
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2.4 Data Flash Read Enable Register (DFLRE) Address: 007F C440h KEY[7:0] Value after reset: — — — — DBRE3 DBRE2 DBRE1 DBRE0 Value after reset: Symbol Bit Name Description DBRE0 DB0 Block Read Enable 0: Read disabled 1: Read enabled...
Page 916: Data Flash Programming/Erasure Enable Register (Dflwe)
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2.5 Data Flash Programming/Erasure Enable Register (DFLWE) Address: 007F C450h KEY[7:0] Value after reset: — — — — DBWE3 DBWE2 DBWE1 DBWE0 Value after reset: Symbol Bit Name Description DBWE0 DB0 Block Programming/Erasure Enable 0: Programming/erasure disabled 1: Programming/erasure enabled...
Page 917: Flash P/E Mode Entry Register (Fentryr)
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2.6 Flash P/E Mode Entry Register (FENTRYR) Address: 007F FFB2h FEKEY[7:0] Value after reset: — — — — — FENTRYD FENTRY1 FENTRY0 Value after reset: Symbol Bit Name Description FENTRY0 ROM P/E Mode Entry 0 See section 26, ROM (Flash Memory for Code Storage).
Page 918 RX610 Group 27. Data Flash (Flash Memory for Data Storage) FENTRYD Bit (Data Flash P/E Mode Entry) The FENTRYD bit is used to place the data flash in P/E mode. [Writing-enable conditions (when all of the following conditions are met)] •...
Page 919: Data Flash Blank Check Control Register (Dflbccnt)
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2.7 Data Flash Blank Check Control Register (DFLBCCNT) Address: 007F FFCAh — — — BCADR[9:0] Value after reset: — — BCSIZE BCADR[9:0] Value after reset: Symbol Bit Name Description BCSIZE Blank Check Size Setting 0: The size of the area to be blank-checked is 8 bytes.
Page 920: Data Flash Blank Check Status Register (Dflbcstat)
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.2.8 Data Flash Blank Check Status Register (DFLBCSTAT) Address: 007F FFCEh — — — — — — — — Value after reset: — — — — — — — BCST Value after reset: Symbol Bit Name...
Page 921: Configuration Of Memory Mat For The Data Flash Memory
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.3 Configuration of Memory Mat for the Data Flash Memory The data flash memory of products in the RX610 Group is configured as a 32-Kbyte data mat. The address range occupied by this mat is shown in figure 27.2.
Page 922: Operating Modes Associated With The Data Flash
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.5 Operating Modes Associated with the Data Flash For the transitions between operating modes, see section 26.5, Operating Modes Associated with the ROM. Reading, programming, and erasing of the data flash memory in an on-board device can proceed if the device is in boot, user-boot, or single-chip mode (with on-chip ROM enabled), or in on-chip-ROM-enabled expansion mode.
Page 923: Programming And Erasing The Data Flash Memory
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.6 Programming and Erasing the Data Flash Memory The data flash memory is programmed and erased by issuing commands to a dedicated sequencer (FCU) for programming and erasure. The FCU has five modes. For programming and erasure, the mode is changed and then commands for programming and erasure are issued.
Page 924: Rom P/E Modes
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.6.1.1 ROM P/E Modes The ROM P/E modes are for programming and erasure of the ROM. For details on the ROM P/E modes, see section 26.6.1.2, ROM P/E Modes. 27.6.1.2 ROM/Data Flash Read Mode This mode is for reading the ROM or data-flash memory.
Page 925: Fcu Commands
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.6.2 FCU Commands FCU commands consist of commands for mode transitions of the FCU and of commands for programming and erasure. Table 27.5 lists the FCU commands for use with the data flash. Table 27.5 FCU Commands for Use with Data Flash Memory Command...
Page 926: Connections Between Fcu Modes And Commands
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.6.3 Connections between FCU Modes and Commands The sets of FCU commands that can be accepted in each of the FCU modes are fixed. Furthermore, which commands are acceptable in a given FCU mode varies according to the state of the FCU. Issuing of an FCU command must follow checking of the FCU's state after transitions of the FCU mode.
Page 927: Fcu Command Usage
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.6.4 FCU Command Usage This section shows how to program and erase the data flash memory by using programming and block erasure commands, respectively, and how to check the state of erasure of the data flash by using the blank check command. For the method for transferring the firmware to the FCU RAM and the ways to use other FCU commands, see section 26.6.4, FCU Command Usage.
Page 928 RX610 Group 27. Data Flash (Flash Memory for Data Storage) Start Write byte E8h to a data flash area address Write the number of programming 8-byte programming: N = 04h words (N) to a data flash area address 128-byte programming: N = 40h through byte access Write a programming data word to the start address of the programming area...
Page 929 RX610 Group 27. Data Flash (Flash Memory for Data Storage) Erasure To erase the data flash, use the block erasure command. The data flash is erased in the same way as the ROM (see section 26, ROM (Flash Memory for Code Storage)). Note that the data flash has a programming and erasure protection function that is controlled by DFLWE.
Page 930 RX610 Group 27. Data Flash (Flash Memory for Data Storage) Start Write 1 to the FRDMD bit in FMODR BCSIZE 0: 8 bytes, 1: 8 Kbytes Set DFLBCCNT BCADR The address of a target area when BCSIZE = 0 Write 71h to the addresses in data flash area in byte units Write D0h to any addresses in the erasure block in byte units...
Page 931: Protection
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.7 Protection There are two types of data flash programming/erasure protection: software protection and error protection. 27.7.1 Software Protection In the software protection function, control register settings are used to disable data flash programming and erasure. If an attempt is made to issue a programming or erasure command for the data flash and the command violates current software protection, the FCU detects the error and enters the command-locked state.
Page 932: Error Protection
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.7.2 Error Protection Error protection is the detection of errors in the issuing of FCU commands and of prohibited access, and response in the form of notification of the FCU malfunction and prohibition of the reception of further commands by the FCU (the FCU enters the command-locked state).
Page 933: Boot Mode
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.8 Boot Mode To program or erase the data mat in boot mode, send control commands and programming data from the host. For the system configuration and settings in boot mode, see section 26.10, Boot Mode. This section describes only the commands dedicated for the data flash.
Page 934 RX610 Group 27. Data Flash (Flash Memory for Data Storage) Data Mat Information Inquiry In response to a data mat information inquiry command sent from the host, the RX610 returns the number of data mat areas and their addresses. Command Response Size Area count...
Page 935: Programming/Erasing Host Commands
RX610 Group 27. Data Flash (Flash Memory for Data Storage) 27.8.2 Programming/Erasing Host Commands Table 27.10 shows the programming/erasing host commands dedicated to the data flash. Data flash-dedicated host commands are provided only for checksum and blank check of the data flash; the programming, erasing, and reading commands are used in common for the ROM and data flash.
Page 936: Usage Notes
RX610 Group 27. Data Flash (Flash Memory for Data Storage) Data Mat Blank Check In response to a data mat blank check command sent from the host, the RX610 checks whether the data mat is completely erased. When the data mat is completely erased, the RX610 returns a response (06h). If the data mat has an unerased area, the RX610 returns an error response (sends E2h and 52h in that order).
Page 937: Features
RX610 Group 28. Boundary Scan Boundary Scan The RX610 Group has boundary scan function, and this function is supported only in the 176-pin LFBGA version. The boundary scan is a serial I/O interface based on the JTAG (Joint Test Action Group, IEEE Std.1149.1 and IEEE Standard Test Access Port and Boundary-Scan Architecture).
Page 938: Register Descriptions
RX610 Group 28. Boundary Scan Table 28.2 shows the I/O pins used in the boundary scan function. Table 28.2 Pin Configuration Pin Name Description Input Test clock input pin Clock signal for boundary scan. Input the clock the duty cycle of which is 50 percent when boundary scan function is used.
Page 939: Instruction Register (Jtir)
RX610 Group 28. Boundary Scan 28.2.1 Instruction Register (JTIR) TS[3:0] Value after reset: Symbol Bit Name Description  The command configuration is as shown in table 28.5. b3 to b0 TS[3:0] Test Bit Set Table 28.5 Command Configuration Instruction EXTEST SAMPLE/PRELOAD IDCODE (initial value) CLAMP...
Page 940 RX610 Group 28. Boundary Scan Table 28.6 Relationship between Pins and JTBSR Bits From TDI 176-Pin LFBGA Pin Name Input/Output Bit Name Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Input...
Page 941 RX610 Group 28. Boundary Scan From TDI 176-Pin LFBGA Pin Name Input/Output Bit Name Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable...
Page 942 RX610 Group 28. Boundary Scan From TDI 176-Pin LFBGA Pin Name Input/Output Bit Name Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable...
Page 943 RX610 Group 28. Boundary Scan From TDI 176-Pin LFBGA Pin Name Input/Output Bit Name Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable...
Page 944 RX610 Group 28. Boundary Scan From TDI 176-Pin LFBGA Pin Name Input/Output Bit Name Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable...
Page 945 RX610 Group 28. Boundary Scan From TDI 176-Pin LFBGA Pin Name Input/Output Bit Name Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable...
Page 946 RX610 Group 28. Boundary Scan From TDI 176-Pin LFBGA Pin Name Input/Output Bit Name Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable...
Page 947 RX610 Group 28. Boundary Scan From TDI 176-Pin LFBGA Pin Name Input/Output Bit Name Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable...
Page 948: Idcode Register (Jtid)
RX610 Group 28. Boundary Scan 28.2.4 IDCODE Register (JTID) Value after reset: Value after reset: Description  JTID is a register with the fixed value that indicates the device IDCODE. b31 to b0 JTID is a 32-bit register. JTID data is output from the TDO pin when the IDCODE instruction has been executed. R01UH0032EJ0120 Rev.1.20 Page 948 of 1006 Feb 20, 2013...
Page 949: Operations
RX610 Group 28. Boundary Scan 28.3 Operations The boundary scan functionality is valid when the EMLE pin is driven low and the BSCANP pin is driven high. 28.3.1 TAP Controller Figure 28.2 shows the state transition diagram of the TAP controller. Test-logic-reset Select-DR Select-IR...
Page 950: List Of Commands
RX610 Group 28. Boundary Scan 28.3.2 List of Commands (1) BYPASS [Instruction Code: 1111b] The BYPASS instruction is an instruction that drives the bypass register (JTBPR). This instruction shortens the shift path, facilitating the transfer of serial data to other LSIs on a printed-circuit board at higher speeds. While this instruction is being executed, the test circuit has no effect on the system circuits.
Page 951 RX610 Group 28. Boundary Scan (5) CLAMP [Instruction Code: 0110b] When the CLAMP instruction is selected, output pins output the boundary scan register value which was specified by the SAMPLE/PRELOAD instruction in advance. While the CLAMP instruction is selected, the status of boundary scan register is maintained regardless of the TAP controller state.
Page 952: Usage Notes
RX610 Group 28. Boundary Scan 28.4 Usage Notes 1. In serial transfer, data are input or output in LSB order (see figure 28.3). JTIR, JTIDR Bit 31 Bit 30 Serial data input/output in Shift register LSB order Bit 1 Bit 0 Figur e 28.3 Ser ial Data I nput/Output 2.
Page 953 RX610 Group 28. Boundary Scan 11. Figure 28.4 (3) shows the pin configuration of pins P66 and P67. When the boundary scan function is used with pins P66 and P67 to be used as DA output pins (DA0 and DA1), the conflict with the DA output or sneak current might be generated.
Page 954: Absolute Maximum Ratings
RX610 Group 29. Electrical Characteristics Electrical Characteristics 29.1 Absolute Maximum Ratings Table 29.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage , PLLV -0.3 to +4.6 Input voltage (except for ports 0, 14 to 17) -0.3 to V +0.3 Input voltage (ports 0, 14 to 17* -0.3 to +6.5...
Page 955: Dc Characteristics
RX610 Group 29. Electrical Characteristics 29.2 DC Characteristics Table 29.2 DC Characteristics Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V REFH REFL = -20 to +85°C (regular specifications), T = -40 to +85°C (wide-range specifications) Item Symbol...
Page 956 RX610 Group 29. Electrical Characteristics Item Symbol Min. Typ. Max. Unit Test Conditions  μA Input pull-up resistor Ports A to E = 3.0 to 3.6 V, current = 0 V   Input capacitance All input pins = 0 V, (except port 0, ports 14 to 17) f = 1 MHz, = 25 C...
Page 957 RX610 Group 29. Electrical Characteristics Table 29.3 Permissible Output Currents Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V REFH REFL = -20 to +85°C (regular specifications), T = -40 to +85°C (wide-range specifications) Item Symbol...
Page 958: Ac Characteristics
RX610 Group 29. Electrical Characteristics 29.3 AC Characteristics Table 29.4 Operation Frequency Value Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V REFH REFL = -20 to +85°C (regular specifications), T = -40 to +85°C (wide-range specifications) Item Symbol...
Page 959 RX610 Group 29. Electrical Characteristics Oscillator ICLK IRQMD[1:0] SSIER.SSIi SSBY IRQ exception Software standby mode IRQ exception handling (power-down mode) handling IRQMD[1:0] = 10b SSBY = 1 Oscillation WAIT instruction settling time OSC2 Figure 29.2 Oscillation Settling Timing after Software Standby Mode R01UH0032EJ0120 Rev.1.20 Page 959 of 1006 Feb 20, 2013...
Page 960 RX610 Group 29. Electrical Characteristics Oscillator ICLK Undefined Invalid by the internal reset IRQ interrupt DIRQnF set request DIRQnEG bit DPSBY bit Cleared When IOKEEP=H IOKEEP bit Cleared I/O port Operating Retained Operating When IOKEEP=L IOKEEP bit I/O port Operating Retained Operating DPSRSTF flag...
Page 961 RX610 Group 29. Electrical Characteristics EXTAL DEXT OSC1 RES# ICLK Figure 29.4 Oscillation Settling Timing EXTAL x 0.5 Figure 29.5 External Input Clock Timing R01UH0032EJ0120 Rev.1.20 Page 961 of 1006 Feb 20, 2013...
Page 962: Control Signal Timing
RX610 Group 29. Electrical Characteristics 29.3.2 Control Signal Timing Table 29.6 Control Signal Timing Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V REFH REFL ICLK = 8 to 100 MHz, BCLK = 8 to 25 MHz = -20 to +85°C (regular specifications), T = -40 to +85°C (wide-range specifications) Test...
Page 963: Bus Timing
RX610 Group 29. Electrical Characteristics 29.3.3 Bus Timing Table 29.7 Bus Timing Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V, BCLK = 8 to 25 MHz REFH REFL = -20 to +85°C (regular specifications), T...
Page 964 RX610 Group 29. Electrical Characteristics CSRWAIT: 2 CSROFF: 1 RDON: 1 CSON: 0 BCLK Byte write strobe mode A23 to A0 1-write strobe mode A23 to A1 BC1#, BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# RD# (Read) D15 to D0 (Read)
Page 965 RX610 Group 29. Electrical Characteristics CSWWAIT: 2 WRON: 1 WDON: 1* CSWOFF: 1 WDOFF: 1* CSON: 0 BCLK Byte write strobe mode A23 to A0 1-write strobe mode A23 to A1 BC1#, BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0# WR0#, WR1#, WR# (Write)
Page 966 RX610 Group 29. Electrical Characteristics CSRWAIT: 2 CSPRWAIT: 2 CSPRWAIT: 2 CSPRWAIT: 2 RDON: 1 RDON: 1 RDON: 1 RDON: 1 CSROFF: 1 CSON: 0 BCLK Byte write strobe mode A23 to A0 1-write strobe mode A23 to A1 BC1#, BC0# Common to both byte write strobe mode and 1-write strobe mode CS7# to CS0#...
Page 967 RX610 Group 29. Electrical Characteristics CSRWAIT: 3 CSWWAIT: 3 BCLK A23 to A0 CS7# to CS0# RD# (Read) WR# (Write) External wait WAIT# Figure 29.13 External Bus Timing/External Wait Control R01UH0032EJ0120 Rev.1.20 Page 967 of 1006 Feb 20, 2013...
Page 968: Timing Of On-Chip Peripheral Modules
RX610 Group 29. Electrical Characteristics 29.3.4 Timing of On-Chip Peripheral Modules Table 29.8 Timing of On-Chip Peripheral Modules (1) Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V, PCLK = 8 to 50 MHz REFH REFL = -20 to +85°C (regular specifications), T...
Page 969 RX610 Group 29. Electrical Characteristics Table 29.8 Timing of On-Chip Peripheral Modules (2) Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V, PCLK = 8 to 50 MHz REFH REFL = -20 to +85°C (regular specifications), T...
Page 970 RX610 Group 29. Electrical Characteristics Table 29.8 Timing of On-Chip Peripheral Modules (3) Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V, REFH REFL = -20 to +85°C (regular specifications), T = -40 to +85°C (wide-range specifications) Test Item...
Page 971 RX610 Group 29. Electrical Characteristics PCLK Ports 0 to E (read) (144-pin LQFP) Ports 0 to H (read) (177-pin LFBGA) Ports 0 to E (write) (144-pin LQFP) Ports 0 to H (write) (177-pin LFBGA) Figure 29.14 I/O Port Input/Output Timing PCLK TOCD Output compare output*...
Page 972 RX610 Group 29. Electrical Characteristics PCLK PO31 to PO0 Figure 29.17 PPG Output Timing PCLK TMOD TMO0 to TMO3 Figure 29.18 8-Bit Timer Output Timing PCLK TMRS TMRI0 to TMRI3 Figure 29.19 8-Bit Timer Reset Input Timing PCLK TMCS TMCS TMCI0 to TMCI3 TMCWL TMCWH...
Page 973 RX610 Group 29. Electrical Characteristics PCLK WOVD WOVD WDTOVF# Figure 29.21 WDT Output Timing SCKW SCKr SCKf SCK0 to SCK6 Scyc Figure 29.22 SCK Clock Input Timing SCK0 to SCK6 TxD0 to TxD6 (Transmit data) RxD0 to RxD6 (Receive data) Figure 29.23 SCI Input/Output Timing: Clock Synchronous Mode PCLK...
Page 974 RX610 Group 29. Electrical Characteristics SDA0, SDA1 SCLH STAS STAH STOS SCL0, SCL1 SCLL SDAS SDAH Test conditions Note: S, P, and Sr represent the following conditions: × × S: Start condition 0.7, V P: Stop condition = 0.6V, I = 6mA (ICFER.FMPE = 0) Sr: Retransmit start condition = 0.4V, I...
Page 975 RX610 Group 29. Electrical Characteristics TMSS TMSH TDIS TDIH TDOD Figure 29.28 Boundary Scan Input/Output Timing R01UH0032EJ0120 Rev.1.20 Page 975 of 1006 Feb 20, 2013...
Page 976: A/D Conversion Characteristics
RX610 Group 29. Electrical Characteristics 29.4 A/D Conversion Characteristics Table 29.9 A/D Conversion Characteristics Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V, PCLK = 8 to 50 MHz, REFH REFL ADCLK = 4 to 50 MHz...
Page 977: Rom (Flash Memory For Code Storage) Characteristics
RX610 Group 29. Electrical Characteristics 29.6 ROM (Flash Memory for Code Storage) Characteristics Table 29.11 ROM (Flash Memory for Code Storage) Characteristics Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V REFH REFL...
Page 978: Data Flash (Flash Memory For Data Storage) Characteristics
RX610 Group 29. Electrical Characteristics 29.7 Data Flash (Flash Memory for Data Storage) Characteristics Table 29.12 Data Flash (Flash Memory for Data Storage) Characteristics Conditions: V = PLLV = AV = 3.0 to 3.6 V, V = 3.0 V to AV = PLLV = 0 V REFH...
Page 979 RX610 Group 29. Electrical Characteristics Write suspend FCU command Program Suspend DSPD FSTATR0.FRDY Ready Not Ready Ready Write pulse Programming Erasure suspend in suspend priority mode FCU command Suspend Erase Suspend Resume SESD2 DSESD2 SESD1 DSESD1 FSTATR0.FRDY Ready Not Ready Ready Not Ready Erasure pulse...
Page 980 RX610 Group Appendix 1. Port States in Each Processing Mode Appendix 1. Port States in Each Processing Mode Table 1.1 Port States in Each Processing State After Deep Software Standby Mode is Canceled Operating Mode Deep Software Standby Mode Software Standby Mode (Return of Start-up Mode) Port Name According to Registers...
Page 981 RX610 Group Appendix 1. Port States in Each Processing Mode After Deep Software Standby Mode is Canceled Operating Mode Deep Software Standby Mode Software Standby Mode (Return of Start-up Mode) Port Name According to Registers IOKEE P = 1/0 Pin Name Setting Reset OPE = 1...
Page 982 RX610 Group Appendix 1. Port States in Each Processing Mode After Deep Software Standby Mode is Canceled Operating Mode Deep Software Standby Mode Software Standby Mode (Return of Start-up Mode) Port Name According to Registers IOKEE P = 1/0 Pin Name Setting Reset OPE = 1...
Page 983 RX610 Group Appendix 1. Port States in Each Processing Mode After Deep Software Standby Mode is Canceled Operating Mode Deep Software Standby Mode Software Standby Mode (Return of Start-up Mode) Port Name According to Registers IOKEE P = 1/0 Pin Name Setting Reset OPE = 1...
Page 984 RX610 Group Appendix 1. Port States in Each Processing Mode After Deep Software Standby Mode is Canceled Operating Mode Deep Software Standby Mode Software Standby Mode (Return of Start-up Mode) Port Name According to Registers IOKEE P = 1/0 Pin Name Setting Reset OPE = 1...
Page 985 RX610 Group Appendix 2. Package Dimensions Appendix 2. Package Dimensions Information on the latest version of the package dimensions or mountings has been displayed in "Packages" on Renesas Technology Corp. website. 176-pin LFBGA (PLBG0176GA-A) R01UH0032EJ0120 Rev.1.20 Page 985 of 1006...
Page 986 RX610 Group Appendix 2. Package Dimensions JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-LQFP144-20x20-0 50 PLQP0144KA-A 144P6Q-A / FP-144L / FP-144LV 1.2g NOTE) DIMENSIONS " *1" AND " *2" DO NOT INCLUDE MOLD FLASH. DIMENSION " *3" DOES NOT INCLUDE TRIM OFFSET.
Page 987 RX610 Group REVISION HISTORY RX610 Group Hardware Manual REVISION HISTORY Description Rev. Data Page Summary − 0.11 Apr 15, 2009 First edition issued 0.12 Aug 07, 2009 1.Overview Table 1.1 Outline of Specifications: Interrupt control unit, changed Table 1.1 Outline of Specifications: Programmable I/O ports, changed Figure 1.2 Block Diagram changed 2.CPU 2.2.2.4 Processor Status Word (PSW): Note 1.
Page 988 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.12 Aug 07, 2009 10.4.1 Enabling and Disabling Interrupts changed 10.4.2 Interrupt Status Flag changed 10.4.2.1 Interrupt Status Flag in Edge Detection changed 10.4.2.2 Interrupt Status Flag in Level Detection changed 10.4.3 Selecting Interrupt Request Destinations changed 10.4.4 Determining Priority changed 10.4.5 Fast Interrupt changed...
Page 989 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.12 Aug 07, 2009 20.2.7 Serial Status Register (SSR) (1) Serial Communications Interface Mode (SMIF in SCMR = 0) 585 to 586 Description on the TEND, PER, FER, and ORER flags changed (2) Smart Card Interface Mode (SMIF in SCMR = 1) 587 to 588 Description on the TEND, PER, and ORER flags changed...
Page 990 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.12 Aug 07, 2009 22.2.17 I2C Bus Bit Rate Low-Level Register (ICBRL) changed 22.2.18 I2C Bus Bit Rate High-Level Register (ICBRH) changed Table 22.6 Examples of ICBRH/ICBRL Settings for Transfer Rate changed 22.2.20 I2C Bus Receive Data Register (ICDRR) changed 22.2.21 I2C Bus Shift Register (ICDRS) changed 688 to 704...
Page 991 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.12 Aug 07, 2009 26.6.2 FCU Commands changed Table 26.6 FCU Commands for Use with the ROM changed Table 26.7 FCU Command Formats changed 26.6.3 Connections between FCU Modes and Commands added 26.6.4 FCU Command Usage changed 26.6.4.1 Mode Transitions changed 26.6.4.2 Programming and Erasure changed...
Page 992 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.12 Aug 07, 2009 28. Electrical Characteristics Table 28.2 DC Characteristics (1): Note 4 added Table 28.9 Timing of On-Chip Peripheral Modules (1) changed Table 28.9 Timing of On-Chip Peripheral Modules (2) changed Table 28.9 Timing of On-Chip Peripheral Modules (3) changed Appendix 1.Port States in Each Processing Mode 878 to 881...
Page 993 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.40 Dec 16, 2009 Section 8 Low Power Consumption (section title changed) Table 8.1 States of Operation, Note 7. added 164, 165 8.2.1 Standby Control Register (SBYCR), bit SSBY: Bit description changed 8.2.5 Deep Standby Control Register (DPSBYCR), bit DPSBY: Bit description changed 8.2.8 Deep Standby Interrupt Flag Register (DPSIFR), Register description changed 8.5.2.1 Transitions to All-Module Clock Stop Mode, changed...
Page 994 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.40 Dec 16, 2009 Section 13 Data Transfer Controller (DTC) Table 13.3 Correspondence between Interrupt Sources, DTC Vector Addresses, and the ISELRn Register of the ICU, changed 13.4.6 Chain Transfer, changed Figure 13.9 Chain Transfer Operation, changed 13.5 DTC Setting Procedure, changed Figure 13.14 Procedure to Set the DTC, changed...
Page 995 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.40 Dec 16, 2009 22.2.2 I C Bus Control Register 2 (ICCR2): Bit allocation: Value after a reset, changed 669 to 672 Bit description changed 22.2.3 I C Bus Mode Register 1 (ICMR1), bits BC[2:0]: Bit description changed 22.2.5 I C Bus Mode Register 3 (ICMR3), bits ACKBR and ACKBT: Bit description changed 22.2.7 I...
Page 996 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.40 Dec 16, 2009 Figure 23.12 Connections between Compare-Match A Signals from TMR0 and TMR2 and the Respective Converter Units, changed 23.6.7 Ranges of Settings for Analog Power Supply and Other Pins, changed Figure 23.16 Example of Connections for AVcc = Vcc and AVss = Vss = VREFL, changed 23.6.8 Point for Caution Regarding Board Design, changed 23.6.9 Point for Caution Regarding Countermeasures for Noise, changed...
Page 997 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 0.40 Dec 16, 2009 26.10 Boot Mode, 26.10.1 System Configuration, changed Figure 26.24 System Configuration for Operations in Boot Mode, changed 843 to 844 26.10.2 ID Code Protection, changed 26.10.3 State Transitions in Boot Mode Figure 26.26 State Transitions in Boot Mode, changed (2) Waiting for a Host Command for Inquiry or Selection, (3) Judging ID Code Protection, (4) Waiting for an ID Code, changed...
Page 998 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 1.00 Mar 16, 2010 10. Interrupt Control Unit (ICU) 10.6.2 Returning from Software Standby Mode, changed 10.7 Usage Notes, added 14. I/O Ports Table 14.1 Specifications of I/O Ports: 176-pin LFBGA added Table 14.2 Port Functions: Description on ports F to H, added Table 14.3 Registers for Each Port: Registers DDR, DR, PORT, and ICR for PF, PG, and PH, added...
Page 999 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 1.00 Mar 16, 2010 29. Electrical Characteristics Table 29.5 Clock Timing: Oscillation settling time after leaving deep software standby mode (crystal), t added OSC3, Figure 29.2 Oscillation Settling Timing after Software Standby Mode, changed Figure 29.3 Oscillation Settling Timing after Deep Software Standby Mode, added Table 29.8 Timing of On-Chip Peripheral Modules (3): Boundary scan added Figure 29.26 Boundary Scan TCK Timing, added...
Page 1000 RX610 Group REVISION HISTORY Description Rev. Data Page Summary 1.10 Apr 05, 2011 11. Buses Table 11.5 Pin Configuration of the External Bus: Note added 11.3.3 CSi Mode Register (CSiMOD): Description on bit WRMOD, changed Table 11.8 Control Signals for Write Access Mode, changed 11.5.5.3 Restrictions in Relation to RMPA and String-Manipulation Instructions: Title and description, changed 11.5.5.5 Restriction on Instruction Code, added...

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