Renesas RZ/G1H User Manual
  1. Manuals
  2. Brands
  3. Renesas Manuals
  4. Microcontrollers
  5. RZ/G1H
  6. User manual

Renesas RZ/G1H User Manual

For rich graphics applications rz/g series
Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
RZ/G1H
User's Manual: Hardware
for Rich Graphics Applications
RZ/G Series
Specifications of Individual RZ/G Series Product
Rev.1.00 Sep 2016

Advertisement

Table of Contents
loading

Related Manuals for Renesas RZ/G1H

Summary of Contents for Renesas RZ/G1H

  • Page 1 RZ/G1H User’s Manual: Hardware for Rich Graphics Applications RZ/G Series Specifications of Individual RZ/G Series Product Rev.1.00 Sep 2016...
  • Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
  • Page 3 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence.
  • Page 4 Make sure to refer to the latest versions of these documents. Document Type Description Document Title Document No. User’s manual Overview of hardware, pin assignments, pin RZ/G1H User’s Manual: R01UH0627EJ0 for specifications multiplexing, and pin function controller Hardware 100 Rev.1.00 of individual (This user’s...
  • Page 5 2. Notation of Numbers and Symbols Bit notation: Bits are shown in high-to-low order from left to right. Number notation: Binary numbers are given as B'XXXX, hexadecimal numbers are given as H'XXXX, and decimal numbers are given as XXXX. Signal notation: A number sign (#) after the name indicates that a signal or pin is active-low, unless otherwise specified.
  • Page 6 3. Register Notation Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. All trademarks and registered trademarks are the property of their respective owners.

  • Page 7: Table Of Contents

    Contents 1. Overview ............................1-1 Introduction ................................1-1 System Configuration Diagram..........................1-2 List of Specifications ............................. 1-3 1.3.1 ARM Core ..............................1-3 1.3.2 CPU Core Peripherals ..........................1-4 1.3.3 External Bus Module ........................... 1-5 1.3.4 Internal Bus Module ............................ 1-7 1.3.5 Local Memory .............................
  • Page 8 5.3.14 Peripheral Function Select Register 6 (IPSR6) ..................5-25 5.3.15 Peripheral Function Select Register 7 (IPSR7) ..................5-26 5.3.16 Peripheral Function Select Register 8 (IPSR8) ..................5-27 5.3.17 Peripheral Function Select Register 9 (IPSR9) ..................5-28 5.3.18 Peripheral Function Select Register 10 (IPSR10) ..................5-29 5.3.19 Peripheral Function Select Register 11 (IPSR11) ..................

  • Page 9: Overview

    • CAN interface. Also, a full implementation of the extremely expandable and Internal AXI bus has been adopted for the RZ/G1H. This bus structure is optimized for maximum system performance, leading to the realization of high-performance and cost-effective premium in-vehicle infotainment systems.

  • Page 10: System Configuration Diagram

    (7 ch) SSIU (10 ch) Gyro ADC I/F DDR3 DBSC3 JTAG Speed-pulse I/F DTCP (2 ch) DARC (12 ch) DDR3 DBSC3 TCON Crypto Engine (2 ch) IMP-X4 SIM card MFIS IR Receiver Figure 1.1 RZ/G1H System Configuration R01UH0627EJ0100 Rev.1.00 Sep 30,2016...

  • Page 11: List Of Specifications

    RZ/G1H 1. Overview List of Specifications 1.3.1 ARM Core Item Description System CPU Cortex-A15 • ARM Cortex-A15 Quad MPCore 1.4 GHz • L1 I/D cache 32/32 KBytes, L2 cache 2 MBytes • NEON /VFPv4 supported • Security extension supported System CPU Cortex-A7 •...

  • Page 12: Cpu Core Peripherals

    Pin function controller (PFC) • Setting multiplexed pin functions for LSI pins Function of the RZ/G1H pin selectable by setting the registers in the PFC module. • Module selection Enable and disable the functions of RZ/G1H LSI pins to which pin functions from multiple pin groups are assigned by setting the registers in the PFC module.

  • Page 13: External Bus Module

    RZ/G1H 1. Overview 1.3.3 External Bus Module Item Description Local bus state • EX-BUS interface: max. 16-bit bus controller • Frequency: 65 MHz or 43.3 MHz (LBSC) • External area divided into several areas and managed — Allocation to space of area 0, area 1, and area 6 or allocation to space of area 0 only is selected at startup time.
  • Page 14 RZ/G1H 1. Overview Item Description LBSC-DMAC • Three channels • Address space: Physical address space • Transfer direction: Peripheral to memory (AXI-bus), memory (AXI-bus) to peripheral • Data packing for peripheral read data: Memory write data length is selectable as transfer data length to memory side.

  • Page 15: Internal Bus Module

    RZ/G1H 1. Overview 1.3.4 Internal Bus Module Item Description AXI-bus • On-chip main bus — Bus protocol : AXI3 with QoS control — Frequency: 260 MHz — Bus width: 256 bits/128 bits • On-chip CPU & GPU main bus — Corelink CCI-400 Cache Coherent Interconnect - r0p3 —...
  • Page 16 RZ/G1H 1. Overview Item Description S3 cache (S3CTRL) • 2 MBytes cache memory for system Direct memory access • 30 channels for ARM domain controller for system • Address space: 4 Gbytes on architecture (SYS-DMAC) • Data transfer length: Byte, word (2 bytes), longword (4 bytes), 8 bytes, 16 bytes, 32 bytes, and 64 bytes •...

  • Page 17: Local Memory

    RZ/G1H 1. Overview Item Description Interrupt controller INTC-SYS — Four interrupt pins which can detect external interrupts (INTC) — Fall/rise/high level/low level detection is selectable — On-chip peripheral interrupts: Priority can be specified for each module — Max. 384 shared peripheral interrupts supported —...
  • Page 18 RZ/G1H 1. Overview Item Description Graphics engine basic Maximum operating clock frequency AXI: 260 MHz functions APB: 65 MHz (R-GP2D)（option） Drawing functions Four-vertex surface drawing, polygon drawing, line drawing, highly-functional thick line drawing, anti- aliasing, BitBLT with raster operations/α blending, α...
  • Page 19 RZ/G1H 1. Overview Item Description Display unit (DU) Display channel Three independently controllable channels Interface • LVDS output: Four lanes × two channels (One of channels (two lanes × 2)) • Digital RGB : Single channel (8-bit precision for each RGB color) LVDS interface (2 ch) •...
  • Page 20 RZ/G1H 1. Overview Item Description Dynamic range • Single channel compression (DRC) • Contrast correction • Optimal contrast extension processing for every domain of a picture. • A higher contrast expansion effect can be acquired compared with the system which controls the whole screen uniformly.
  • Page 21 RZ/G1H 1. Overview Item Description IMR-X2（option） • Two channels • Pixel pipelines internally operate at the 260-MHz clock frequency (pixels are generated and distortion is corrected at one pixel per two cycles). • Reads data from the external memory, corrects distortion in the data, then outputs the corrected data to the external memory.

  • Page 22: Video Processing

    1. Overview 1.3.7 Video Processing Item Description The VSP1 is the successor IP of Renesas’ VIO6-IP series, and has the following features. Video signal processor 1 (VSP1) (1) Supports various data formats and conversion — Supports YCbCr444/422/420, RGB, αRGB, αplane —...
  • Page 23 RZ/G1H 1. Overview Item Description Fine display processor 1 The FDP1 is the de-interlacing module which converts the interlaced video to progressive (FDP1) video, and has the following features. (1) Supports three channels (2) Supports various data formats — Input: YCbCr444/422/420 —...

  • Page 24: Sound Interface

    RZ/G1H 1. Overview 1.3.8 Sound Interface Item Description Sampling rate converter Overall • Includes ten SRC modules unit (SCU) specification — Supports the quality suitable for audio sound (THD+N -132dB): six modules — Supports the quality suitable for voice sound (THD+N -96dB): four modules •...
  • Page 25 RZ/G1H 1. Overview Item Description Serial sound interface unit Overall • Includes ten SSI modules functioning as interfaces with external (SSIU) specification devices. — Supports short and long formats — Supports TDM format (six modules of ten modules can be used for this function) •...

  • Page 26: Storage

    RZ/G1H 1. Overview 1.3.9 Storage Item Description USB2.0 host & • Three channels (Host only two channel/Host-Function one channel selected)* function module • PHY integrated (USB2.0) • USB Host (EHCI/OHCI) 2LINK • Compliance with USB2.0 • USB Function 1LINK • Compliance with USB2.0 (High-Speed) •...

  • Page 27: Network

    RZ/G1H 1. Overview 1.3.10 Network Item Description CAN interface • Two interfaces (CAN) • Supports CAN specification 2.0B • ISO-11898-1 compliant • Maximum bit rate: 1 Mbps • Message box — Normal mode: 32 receive-only mailboxes and 32 mailboxes for transmission/reception —...
  • Page 28 RZ/G1H 1. Overview Item Description Timer pulse unit • 4-channels (TPU) • 16-bit timers • Each channel outputs PWM Compare match timer • Two channels 0 (CMT0) • 32-bit timer (16 bits/32 bits can be selected) • Source clock: RCLK clock •...

  • Page 29: Peripheral Module

    RZ/G1H 1. Overview 1.3.12 Peripheral Module Item Description I2C bus interface (IIC) • Four channels • One of channel (Channel3) for DVFS • Supports single master transmission/reception • Interrupt request • DMAC request • IIC pins switchable with I2C pins (just below) Multi-master I2C bus •...
  • Page 30 RZ/G1H 1. Overview Item Description Serial communication Overall • Three channels interface with FIFO specification • Asynchronous, clock-synchronized modes (SCIF) • Asynchronous serial communication mode The SCIF performs serial data communication based on a character-by- character asynchronous system. This feature enables serial data...

  • Page 31: Others

    RZ/G1H 1. Overview Item Description Clock-synchronized • Four channels serial interface with • Max. speed: 26 MHz (ch 2 only), 13 MHz (ch 0, 1, and 3) FIFO (MSIOF) • Internal 64-byte transmit FIFOs/internal 256-byte receive FIFOs • Supports master and slave modes •...

  • Page 32: Power Supply Voltages And Temperature Range

    RZ/G1H 1. Overview Power Supply Voltages and Temperature Range • Power supply voltage (typ.) 1.8 V: (ETM, SDHI, DDR3_GPIO, LVCMOS I/F, Xtal, JTAG, and RST) 1.03 V: (Core, SATA/USB3.0/PCI Express-I/O) 1.5 V: (DDR3-I/O SSTL mode: DDR3) 3.3 V: (Others) •...

  • Page 33: Package

    RZ/G1H 1. Overview Package φ φ× S AB × Index mark Dimension in Millimeters Reference Symbol DIM. IN mm Max. Min. Nom. 27.0 27.0 0.15 0.20 0.35 0.45 0.45 0.55 0.08 0.15 Figure 1.2 Package Outline R01UH0627EJ0100 Rev.1.00 1-25 Sep 30,2016...

  • Page 34: Area Map

    RZ/G1H 2. Area Map 2. Area Map See section 2, Area Map in the RZ/G Series User’s Manual: Hardware. R01UH0627EJ0100 Rev.1.00 Sep 30,2016...

  • Page 35: Pin Assignment

    RZ/G1H 3. Pin Assignment 3. Pin Assignment Top View (Left) VDDQ_ VDDQ_ VDDQ_ M1DQ31 M1DQ29 M1DM3 M1DQ28 M1DQ17 M1DQ21 M1DQ3 M1DM0 M1DQ8 M1DQ9 M1DQ15 M0A8 M1A0 M1DQ24 M1DQ30 M1DQ16 M1DQ19 M1DQ23 M1DQ1 M1DQ0 M1DQ11 M1DQ13 M0A14 VDDQ_ M1BA1 M1A12 M1DQ26...

  • Page 36: Top View (Right)

    RZ/G1H 3. Pin Assignment Top View (Right) VDDQ_ VDDQ_ VDDQ_ M0A13 M0A11 M0CS1# M0A4 M0A2 M0DQ9 M0DQ15 M0DQ0 M0DM0 M0DQ3 M0DQ7 M0A6 M0A9 M0CS0# M0A7 M0A1 M0DQ8 M0DQ14 M0DQ12 M0DQ4 M0DQ5 M0DQ19 M0A10 M0CKE1 M0BA0 M0CAS# M0DQ10 M0DM1 M0DQ6 M0DQ1...

  • Page 37: Mode Pin Settings

    RZ/G1H 3. Pin Assignment Mode Pin Settings Input fixed values for the MPMD0, MPMD1, and BSMODE pins. These values cannot be changed after power is supplied. The values of pins MD0 to MD28, MDT0 and MDT1 are input upon power-on reset using the PRESET# pin.
  • Page 38 RZ/G1H 3. Pin Assignment Master Boot Processor Selection CA15 boot CA7 boot Setting prohibited Setting prohibited EXBUS Area 0 Data Bus Width 8-bit 16-bit EXTAL/XTAL Pin Setting Inputs an external clock to the EXTAL pin. Connects a crystal resonator to the EXTAL/XTAL pin.
  • Page 39 RZ/G1H 3. Pin Assignment Internal External PLL3/ PLL3/ MD14 MD13 Clock Clock PLL1 PLL0 MD19: DDR3-1600 MD19: DDR3-1333 15 MHz × 1/1* × 208* × 172 × 106 (VCO = 1590 MHz) × 88 (VCO = 1320 MHz) 20 MHz ×...
  • Page 40 RZ/G1H 3. Pin Assignment MD24 ComboPHY0 Function Selection SATA-1 PCI express MD26 and MD25 Reserved, fixed to 00 R01UH0627EJ0100 Rev.1.00 Sep 30,2016...

  • Page 41: Pin Multiplexing

    4. Pin Multiplexing 4. Pin Multiplexing List of Multiplexed Pin Functions Table 4.1 lists the multiplexed pin functions of the RZ/G1H. The default pin function of each pin after power-on reset is "Function 1" respectively, unless otherwise mentioned in each table note.
  • Page 42 RZ/G1H 4. Pin Multiplexing Table 4.1 List of Multiplexed Pin Functions DBSC3 channel 0 (No.1 to 60): Single Function Function 1 Function 1 Function 1 Module During POR Module During POR Module During POR Pin No. Pin Name V/|IOH| Pin No. Pin Name V/|IOH| Pin No.
  • Page 43 RZ/G1H 4. Pin Multiplexing DBSC3 channel 0 (No.61 to 93): Single Function Function 1 Function 1 Function 1 Module During POR Module During POR Module During POR Pin No. Pin Name V/|IOH| Pin No. Pin Name V/|IOH| Pin No. Pin Name...
  • Page 44 RZ/G1H 4. Pin Multiplexing DBSC3 channel 1 (32-bit)/DBSC3 channel 0 (64-bit)/DDR3 GPIO (No.94 to 113): Up to 3-Function Multiplexed Pin state during power-on reset and default pin function are defined by the MD28, MD 27, MD22 and MD17 pins setting, which function cannot be changed after power-on reset by software.
  • Page 45 RZ/G1H 4. Pin Multiplexing DBSC3 channel 1 (32-bit)/DBSC3 channel 0 (64-bit)/DDR3 GPIO (No.114 to 133): Up to 3-Function Multiplexed Pin state during power-on reset and default pin function are defined by the MD28, MD 27, MD22 and MD17 pins setting, which function cannot be changed after power-on reset by software.
  • Page 46 RZ/G1H 4. Pin Multiplexing DBSC3 channel 1 (32-bit)/DBSC3 channel 0 (64-bit)/DDR3 GPIO (No.134 to 153): Up to 3-Function Multiplexed Pin state during power-on reset and default pin function are defined by the MD28, MD 27, MD22 and MD17 pins setting, which function cannot be changed after power-on reset by software.
  • Page 47 RZ/G1H 4. Pin Multiplexing DBSC3 channel 1 (32-bit)/DBSC3 channel 0 (64-bit)/DDR3 GPIO (No.154 to 173): Up to 3-Function Multiplexed Pin state during power-on reset and default pin function are defined by the MD28, MD 27, MD22 and MD17 pins setting, which function cannot be changed after power-on reset by software.
  • Page 48 RZ/G1H 4. Pin Multiplexing DBSC3 channel 1 (32-bit)/DBSC3 channel 0 (64-bit)/DDR3 GPIO (No.174 to 188): Up to 3-Function Multiplexed Pin state during power-on reset and default pin function are defined by the MD28, MD 27, MD22 and MD17 pins setting, which function cannot be changed after power-on reset by software.
  • Page 49 RZ/G1H 4. Pin Multiplexing CPG, RESET, SYSTEM, AVS, POWER ISO and GPIO (No.189 to 207): Up to 2-Function Multiplexed Function 1 GPIO Module During POR Pin No. Pin Name V/|IOH| Pull-up AL12 EXTAL 1.8V/- AL13 XTAL 1.8V/- AF12 EXREFIN* 1.8V/-...
  • Page 50 RZ/G1H 4. Pin Multiplexing LBSC, MSIOF, VIN, SCIFB, SCIF, IIC, I2C, TMU, EtherAVB and GPIO (No.208 to 223): Up to 10-Function Multiplexed Default pin function (function 1 or GPIO) after power-on reset is defined by MD[3:1] pins setting. Function 1 GPIO ≠...
  • Page 51 RZ/G1H 4. Pin Multiplexing LBSC, PWM, MSIOF, TPU, SCIFA, ADG, SSI, VIN, SCIFB, SCIF and GPIO (No.224 to 237): Up to 11-Function Multiplexed and Mode Pins assigned (No.224 to 231) Default pin function (function 1 or GPIO) after power-on reset is defined by MD[3:1] pins setting.
  • Page 52 RZ/G1H 4. Pin Multiplexing LBSC, PWM, MSIOF, TPU, SCIFA, ADG, SSI, VIN, SCIFB, SCIF and GPIO (No.238 to 255): Up to 9-Function Multiplexed and Mode Pin Assigned (No.238 to 243) Default pin function (function 1 or GPIO) after power-on reset is defined by MD[3:1] pins setting except for No.253 to 255.
  • Page 53 RZ/G1H 4. Pin Multiplexing LBSC, PWM, MSIOF, TPU, SCIFA, ADG, SSI, VIN, SCIFB, SCIF and GPIO (No.256 to 270): Up to 9-Function Multiplexed and Mode Pin Assigned (No.259 and 260) Default pin function (function 1 or GPIO) after power-on reset is defined by MD[3:1] pins setting except for No.256 to 258, 261 and No.265 to 270.
  • Page 54 RZ/G1H 4. Pin Multiplexing EtherMAC, IIC, I2C, SCIFB, SCIF, HSCIF, SCIFA and GPIO (No.271 to 285): Up to 10-Function Multiplexed and Mode Pin Assigned (No.278 to 284) These pins are set for GPIO after power-on reset. For details, refer to GPSR2 and GPSR5 registers in section 5, Pin Function Controller (PFC).
  • Page 55 RZ/G1H 4. Pin Multiplexing INTC and Debugging Function (No.286 to 292): Single Function Function 1 Module During POR Pin No. Pin Name V/|IOH| Pull-up INTC I(S) AG12 1.8V/- I(S) AG16 TRST# 1.8V/- AE14 1.8V/- AF14 1.8V/4mA IO(I) AH14 1.8V/- AH12 1.8V/8mA...
  • Page 56 RZ/G1H 4. Pin Multiplexing DU_LVDS0, DU_LVDS1 and GPIO (No.293 to 318): Up to 2-Function Multiplexed These pins are set for Function 1 except for No.303. Function 1 GPIO Function 1 Module During POR Module During POR Pin No. Pin Name V/|IOH| Pin No.
  • Page 57 RZ/G1H 4. Pin Multiplexing DU, DU_LVDS1, ADG, VIN, LBSC, EtherAVB and GPIO (No.319 to 334): Up to 5-Function Multiplexed These pins are set for GPIO except for No.320 to 325. For details, refer to GPSR5 and GPSR2 registers in section 5, Pin Function Controller (PFC).
  • Page 58 RZ/G1H 4. Pin Multiplexing VIN, EtherAVB, SCIFA, SDHI0, SCIFB and GPIO (No.335 to 349): Up to 5-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR2 and GPSR3 registers in section 5, Pin Function Controller (PFC).
  • Page 59 RZ/G1H 4. Pin Multiplexing SDHI0/1, MMC, USB2.0, VIN, IIC, I2C, EtherAVB, SCIFB and GPIO (No.350 to 361): Up to 11-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR2 and GPSR3 registers in section 5, Pin Function Controller (PFC).
  • Page 60 RZ/G1H 4. Pin Multiplexing SDHI2, MMC, VIN, SCIFB, SCIF, HSCIF, USB2.0 and GPIO (No.362 to 370): Up to 11-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR3 register in section 5, Pin Function Controller (PFC).
  • Page 61 RZ/G1H 4. Pin Multiplexing SDHI3, MMC and GPIO (No.371 to 379): Up to 11-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR3 register in section 5, Pin Function Controller (PFC). Function 1 GPIO...
  • Page 62 RZ/G1H 4. Pin Multiplexing IIC, I2C, SCIFB, SCIF, RCAN, SSI, MSIOF and GPIO (No.393 to 409): Up to 7-Function Multiplexed These pins are set for GPIO after power-on reset except for No.396 to 398. For details, refer to GPSR4 register in section 5, Pin Function Controller (PFC).
  • Page 63 RZ/G1H 4. Pin Multiplexing SSI, SCIFB, DU, RCAN, SCIF, SCIFA, TMU, ADG, SCU and GPIO (No.410 to 422): Up to 13-Function Multiplexed These pins are set for GPIO after power-on reset. For details, refer to GPSR4 register in section 5, Pin Function Controller (PFC).
  • Page 64 RZ/G1H 4. Pin Multiplexing SCIFA, HSCIF, SCIF, MSIOF, DU, IIC, I2C, PWM and GPIO (No.423 to 434): Up to 10-Function Multiplexed and Mode Pin Assigned (No.425, 427, 429 and 431) These pins are set for GPIO after power-on reset. For details, refer to GPSR4 and GPSR5 registers in section 5, Pin Function Controller (PFC).
  • Page 65 RZ/G1H 4. Pin Multiplexing HSCIF,, DU, SSI, MSIOF, ADG, SCIFA, IIC, I2C and GPIO (No.435 to 449): Up to 8-Function Multiplexed and Mode Pin Assigned (No.437 and No.442 to 444) These pins are set for GPIO after power-on reset except for No.446 to 449. For details, refer to GPSR5 register in section 5, Pin Function Controller (PFC).
  • Page 66 RZ/G1H 4. Pin Multiplexing USB, ADG, TMU and GPIO (No.450 to 487): Up to 3-Function Multiplexed These pins are set for USB after power-on reset. For details, refer to GPSR5 register in section 5, Pin Function Controller (PFC). Function 1...
  • Page 67 RZ/G1H 4. Pin Multiplexing SATA, PCIEC and USB3.0 (No.488 to 529): 2-Function Multiplexed These pins function depends on the MD[24:23] pins setting, and cannot be changed after power-on reset by software. Function 1 Function 2 Function 1 Function 2 MD24 = 0...
  • Page 68 RZ/G1H 4. Pin Multiplexing Thermal Sensor (No.530 and No.531): Single Function Function 1 Function 1 Module During POR Module During POR Pin No. Pin Name V/|IOH| Pin No. Pin Name V/|IOH| Pull-up Pull-up Thermal Sensor Thermal Sensor VTHSENSE0 1.8V/- VTHREF0 1.8V/-...

  • Page 69: Pin States

    RZ/G1H 4. Pin Multiplexing Pin States Table 4.2 is pin state of the RZ/G1H. [Legend] No.: Serial number, Pin No.: BGA package ball grid number, Pin Name: Pin name of function 1 in pin in Table 4.1, I/O: Input or output direction considered about all multiplexed pin functions of the pin.
  • Page 70 RZ/G1H 4. Pin Multiplexing Table 4.2 Pin States During Default Default Pin Name (Function 1) Default Pin Function State Pull-up M0CKE0 M0CKE0 M0CKE1 M0CKE1 M0VREFCA(VSS) M0VREFCA(must be connected to VSS) M0BKPRST# M0BKPRST# M0RESET# M0RESET# H to L M0CK0 M0CK0 M0CK0#...
  • Page 71 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up M0DM0 M0DM0 VDDQ_M0DPLL0 VDDQ_M0DPLL0 VSSQ_M0DPLL0 VSSQ_M0DPLL0 M0VREFDQ0 M0VREFDQ0 M0DQ8 M0DQ8 M0DQ9 M0DQ9 M0DQ10 M0DQ10 M0DQ11 M0DQ11 M0DQ12 M0DQ12 M0DQ13 M0DQ13 M0DQ14 M0DQ14 M0DQ15 M0DQ15...
  • Page 72 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up M1CK0 M1CK0/Reserved* M1CK0# M1CK0#/Reserved* M1CK1 M1CK1/Reserved* M1CK1# M1CK1#/Reserved* M1CS0# M1CS0#/GP_DDR5* M1CS1# M1CS1#/GP_DDR8* M1ODT0 M1ODT0/GP_DDR6* M1ODT1 M1ODT1/GP_DDR10* M1ZQ M1ZQ M1WE# M1WE#/GP_DDR9* M1RAS# M1RAS#/GP_DDR12* M1CAS# M1CAS#/GP_DDR4*...
  • Page 73 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up M1DQ9 M1DQ9/M0DQ41/Reserved* Z/Z/Z M1DQ10 M1DQ10/M0DQ42/Reserved* Z/Z/Z M1DQ11 M1DQ11/M0DQ43/Reserved* Z/Z/Z M1DQ12 M1DQ12/M0DQ44/Reserved* Z/Z/Z M1DQ13 M1DQ13/M0DQ45/Reserved* Z/Z/Z M1DQ14 M1DQ14/M0DQ46/Reserved* Z/Z/Z M1DQ15 M1DQ15/M0DQ47/Reserved* Z/Z/Z M1DQS1 M1DQS1/M0DQS5/Reserved* Z/Z/Z** -...
  • Page 74 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up VSS_CPGPLL3 VSS_CPGPLL3 AF16 PRESET# I(L) PRESET# PRESETOUT# PRESETOUT# L to H AE15 MPMD0 MPMD0 AJ14 MPMD1 MPMD1 AE13 BSMODE BSMODE AA25 AVS1 AVS1 H or L*...
  • Page 75 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up A25/GP1_9* CLKOUT CLKOUT CS0# CS0#/GP1_10* CS1#/A26 [CS1#/A26]/GP1_11* [H or EX_CS0# GP1_12 EX_CS1# GP1_13 EX_CS2# GP1_14 EX_CS3# GP1_15 EX_CS4# GP1_16 EX_CS5# GP1_17 I(MD13) BS#/GP1_18* I(MD16) RD#/GP1_19*...
  • Page 76 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up AG19 DU_LVDS0_CH1_P DU_LVDS0_CH1_P AG20 DU_LVDS0_CH1_N DU_LVDS0_CH1_N AL18 DU_LVDS0_CH2_P DU_LVDS0_CH2_P AL17 DU_LVDS0_CH2_N DU_LVDS0_CH2_N AJ17 DU_LVDS0_CH3_P DU_LVDS0_CH3_P AJ16 DU_LVDS0_CH3_N DU_LVDS0_CH3_N GP5_26 AJ13 DU_DOTCLKIN0 AD18 VDDQ_LVDS VDDQ_LVDS...
  • Page 77 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up SD0_DAT1 GP3_3/TMS2* Off/-* SD0_DAT2 GP3_4/TDI2* Off/-* SD0_DAT3 GP3_5* Off/-* SD0_CD GP3_6 SD0_WP GP3_7 VCCQ_SD0 VCCQ_SD0 SD1_CLK I/Z*7 I/Z*7 Off/-* GP3_8/TDO3* SD1_CMD Off/-* GP3_9/TRST3#* SD1_DAT0...
  • Page 78 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up AA27 VDD_MLBPLL VDD_MLBPLL AA26 VSS_MLBPLL VSS_MLBPLL SSI_SCK0129 GP4_3 SSI_WS0129 GP4_4 SSI_SDATA0 GP4_5 SSI_SDATA1 GP4_6 SSI_SDATA2 GP4_7 SSI_SCK34 GP4_8 SSI_WS34 GP4_9 SSI_SDATA3 GP4_10 SSI_SCK4 GP4_11...
  • Page 79 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up AF15 IIC0_SDA IIC0_SDA AJ15 IIC3_SCL IIC3_SCL AH15 IIC3_SDA IIC3_SDA AL14 USB_EXTAL USB_EXTAL AL15 USB_XTAL USB_XTAL AC24 AVSS AVSS AD25 AVSS AVSS AE26 AVSS AVSS...
  • Page 80 RZ/G1H 4. Pin Multiplexing During Default Default Pin Name (Function 1) Default Pin Function State Pull-up AF24 VDDA_SATA1 VDDA_SATA1/VDDA_PCIe* AG24 VDDA_SATA1 VDDA_SATA1/VDDA_PCIe* AG23 VDDD_SATA1 VDDD_SATA1/VDDD_PCIe* AH24 VDDD_SATA1 VDDD_SATA1/VDDD_PCIe* AE24 VSS_SATA1 VSS_SATA1/VSS_PCIe* AJ24 VSS_SATA1 VSS_SATA1/VSS_PCIe* AK23 VSS_SATA1 VSS_SATA1/VSS_PCIe* AK24 VSS_SATA1 VSS_SATA1/VSS_PCIe*...
  • Page 81 RZ/G1H 4. Pin Multiplexing 6. No.252 CS1#/A26: Default state MD4 = 0: (64-Mbyte mode): high output MD4 = 1: (128-Mbyte mode): low output 7. No.344 and 353: Default state "I" is in function mode (SDHI), "Z" is in debug mode.

  • Page 82: Handling Of Unused Pins

    4. Pin Multiplexing Handling of Unused Pins Table 4.3 shows a handling of unused pins of the RZ/G1H. "Unused pin" means all pin functions of the pin are unused and all modules that have the pin are unused in this section.
  • Page 83 RZ/G1H 4. Pin Multiplexing Table 4.3 Handling of Unused Pins Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M0CKE0 Open M0CKE1 Open M0VREFCA(VSS) Must be used M0BKPRST# Pulled-up to VDDQ_M0BKUP or pulled-down to VSS...
  • Page 84 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M0DM0 Open VDDQ_M0DPLL0 Must be used VSSQ_M0DPLL0 Must be used M0VREFDQ0 Must be used M0DQ8 Open M0DQ9 Open M0DQ10 Open...
  • Page 85 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M1CK0 Open M1CK0# Open M1CK1 Open M1CK1# Open M1CS0# Open M1CS1# Open M1ODT0 Open M1ODT1 Open M1ZQ Must be used...
  • Page 86 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use M1DQ9 Open M1DQ10 Open M1DQ11 Open M1DQ12 Open M1DQ13 Open M1DQ14 Open M1DQ15 Open M1DQS1 Open M1DQS1# Open M1DM1 Open...
  • Page 87 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use VSS_CPGPLL3 Must be used AF16 PRESET# Must be used PRESETOUT# L to H Open AE15 MPMD0 Must be used (pulled-down to VSS)
  • Page 88 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use QSPI* Open CLKOUT Area 0* Open CS0# Area 0* Open [CS1#/A26] [O]/I Area 0* Open EX_CS0# Open EX_CS1# Open EX_CS2#...
  • Page 89 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use Open AG20 DU_LVDS0_CH1_N Open AL18 DU_LVDS0_CH2_P Open AL17 DU_LVDS0_CH2_N Open AJ17 DU_LVDS0_CH3_P Open AJ16 DU_LVDS0_CH3_N Open AJ13 DU_DOTCLKIN0 Must be used...
  • Page 90 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use SD0_DAT2 Pulled-up to VCCQ or pulled-down to VSS SD0_DAT3 Pulled-up to VCCQ or pulled-down to VSS SD0_CD Pulled-up to VCCQ or pulled-down to VSS...
  • Page 91 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AA26 VSS_MLBPLL Must be used SSI_SCK0129 Open SSI_WS0129 Open SSI_SDATA0 Open SSI_SDATA1 Open SSI_SDATA2 Open SSI_SCK34 Open SSI_WS34 Open SSI_SDATA3...
  • Page 92 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AJ15 IIC3_SCL Pulled-up to VCCQ18 AH15 IIC3_SDA Pulled-up to VCCQ18 AL14 USB_EXTAL Pulled-down to VSS AL15 USB_XTAL Open AC24 AVSS...
  • Page 93 RZ/G1H 4. Pin Multiplexing Default Mode Default Pin Name (Function 1) State Boot Pull-up Pin Handling when not in Use AG24 VDDA_SATA1 Must be used AG23 VDDD_SATA1 Must be used AH24 VDDD_SATA1 Must be used AE24 VSS_SATA1 Must be used...

  • Page 94: Pin Function Controller (Pfc)

    • Module selection Enable and disable the functions of RZ/G1H LSI pins to which pin functions from multiple pin groups are assigned by setting the registers in the PFC module. (Selection is handled by the module select register (MOD_SEL), module select register 2 (MOD_SEL2), and module select register 3 (MOD_SEL3).

  • Page 95: Register Configuration

    RZ/G1H 5. Pin Function Controller (PFC) Register Configuration All the registers in the PFC are mapped into the APB bus space. Table 5.1 shows the configuration of the registers provided in the PFC. For details on the registers of the PFC, see section 5.3, Register Description.
  • Page 96 RZ/G1H 5. Pin Function Controller (PFC) Access Name Abbr. Initial Value Address Size Condition Peripheral function select IPSR6 H'0000 0000 H'E606 0038 — register 6 Peripheral function select IPSR7 H'0000 0000 H'E606 003C — register 7 Peripheral function select IPSR8...
  • Page 97 RZ/G1H 5. Pin Function Controller (PFC) Access Name Abbr. Initial Value Address Size Condition DDR3 general port output DDR3GPOE H'0000 0000 H'E606 0244 — enable register DDR3 general port output DDR3GPOD H'0000 0000 H'E606 0248 — data register DDR3 general port input...

  • Page 98: Register Description

    RZ/G1H 5. Pin Function Controller (PFC) Register Description [Legend] Initial value: Register value after a reset Undefined value R/W: Readable/writable. The written value can be read. Read-only. The write value should always be 0. R/WC0: Readable/writable. Writing 0 initializes the bit. Writing 1 is ignored.

  • Page 99: Lsi Multiplexed Pin Setting Mask Register (Pmmr)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.1 LSI Multiplexed Pin Setting Mask Register (PMMR) Function: PMMR enables/disables writing to the multiplexed pin setting registers. Bit: Initial value: R/W: Bit: Initial value: R/W: Bit Name Initial Value Description 31 to 0...

  • Page 100: Gpio/Peripheral Function Select Register 0 (Gpsr0)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.2 GPIO/Peripheral Function Select Register 0 (GPSR0) Function: GPSR0 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 101 RZ/G1H 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP0[24] GP-0-24 Peripheral function selected by IP2[21:18] GP0[25] GP-0-25 Peripheral function selected by IP2[25:22] GP0[26] GP-0-26 Peripheral function selected by IP2[28:26]...

  • Page 102: Gpio/Peripheral Function Select Register 1 (Gpsr1)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.3 GPIO/Peripheral Function Select Register 1 (GPSR1) Function: GPSR1 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 103 RZ/G1H 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP1[24] GP-1-24 Peripheral function selected by IP5[29:27] GP1[25] GP-1-25 Peripheral function selected by IP6[2:0] GP1[26] GP-1-26 Peripheral function selected by IP6[5:3]...

  • Page 104: Gpio/Peripheral Function Select Register 2 (Gpsr2)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.4 GPIO/Peripheral Function Select Register 2 (GPSR2) Function: GPSR2 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 105 RZ/G1H 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP2[25] GP-2-25 Peripheral function selected by IP7[5:3] GP2[26] GP-2-26 Peripheral function selected by IP7[7:6] GP2[27] GP-2-27 Peripheral function selected by IP7[9:8]...

  • Page 106: Gpio/Peripheral Function Select Register 3 (Gpsr3)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.5 GPIO/Peripheral Function Select Register 3 (GPSR3) Function: GPSR3 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 107 RZ/G1H 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP3[25] GP-3-25 Peripheral function selected by IP11[6:5] GP3[26] GP-3-26 Peripheral function selected by IP11[8:7] GP3[27] GP-3-27 Peripheral function selected by IP11[10:9]...

  • Page 108: Gpio/Peripheral Function Select Register 4 (Gpsr4)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.6 GPIO/Peripheral Function Select Register 4 (GPSR4) Function: GPSR4 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 109 RZ/G1H 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP4[25] GP-4-25 Peripheral function selected by IP13[30:29] GP4[26] GP-4-26 Peripheral function selected by IP14[2:0] GP4[27] GP-4-27 Peripheral function selected by IP14[5:3]...

  • Page 110: Gpio/Peripheral Function Select Register 5 (Gpsr5)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.7 GPIO/Peripheral Function Select Register 5 (GPSR5) Function: GPSR5 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...
  • Page 111 RZ/G1H 5. Pin Function Controller (PFC) Bit Name GPIO (Set Value = 0) Peripheral Function (Set Value = 1) GP5[25] GP-5-25 AVS2 GP5[26] GP-5-26 DU_DOTCLKIN0 GP5[27] GP-5-27 Peripheral function selected by IP7[26:25] GP5[28] GP-5-28 DU_DOTCLKIN2 GP5[29] GP-5-29 Peripheral function selected by IP7[18:16]...

  • Page 112: Peripheral Function Select Register 0 (Ipsr0)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.8 Peripheral Function Select Register 0 (IPSR0) Function: IPSR0 selects the functions of the multiplexed LSI pins. Bit: — [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 113: Peripheral Function Select Register 1 (Ipsr1)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.9 Peripheral Function Select Register 1 (IPSR1) Function: IPSR1 selects the functions of the multiplexed LSI pins. Bit: — — [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 114: Peripheral Function Select Register 2 (Ipsr2)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.10 Peripheral Function Select Register 2 (IPSR2) Function: IPSR2 selects the functions of the multiplexed LSI pins. Bit: — — — [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 115: Peripheral Function Select Register 3 (Ipsr3)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.11 Peripheral Function Select Register 3 (IPSR3) Function: IPSR3 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 116: Peripheral Function Select Register 4 (Ipsr4)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.12 Peripheral Function Select Register 4 (IPSR4) Function: IPSR4 selects the functions of the multiplexed LSI pins. Bit: — — [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 117: Peripheral Function Select Register 5 (Ipsr5)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.13 Peripheral Function Select Register 5 (IPSR5) Function: IPSR5 selects the functions of the multiplexed LSI pins. Bit: — — [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 118: Peripheral Function Select Register 6 (Ipsr6)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.14 Peripheral Function Select Register 6 (IPSR6) Function: IPSR6 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 119: Peripheral Function Select Register 7 (Ipsr7)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.15 Peripheral Function Select Register 7 (IPSR7) Function: IPSR7 selects the functions of the multiplexed LSI pins. Bit: — [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 120: Peripheral Function Select Register 8 (Ipsr8)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.16 Peripheral Function Select Register 8 (IPSR8) Function: IPSR8 selects the functions of the multiplexed LSI pins. Bit: — [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 121: Peripheral Function Select Register 9 (Ipsr9)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.17 Peripheral Function Select Register 9 (IPSR9) Function: IPSR9 selects the functions of the multiplexed LSI pins. Bit: [31] [30] [29] [28] [27] [26] [25] [24] [23] [22] [21] [20] [19] [18] [17] [16]...

  • Page 122: Peripheral Function Select Register 10 (Ipsr10)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.18 Peripheral Function Select Register 10 (IPSR10) Function: IPSR10 selects the functions of the multiplexed LSI pins. Bit: IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 IP10 — —...

  • Page 123: Peripheral Function Select Register 11 (Ipsr11)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.19 Peripheral Function Select Register 11 (IPSR11) Function: IPSR11 selects the functions of the multiplexed LSI pins. Bit: IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11 IP11...

  • Page 124: Peripheral Function Select Register 12 (Ipsr12)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.20 Peripheral Function Select Register 12 (IPSR12) Function: IPSR12 selects the functions of the multiplexed LSI pins. Bit: IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 IP12 —...

  • Page 125: Peripheral Function Select Register 13 (Ipsr13)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.21 Peripheral Function Select Register 13 (IPSR13) Function: IPSR13 selects the functions of the multiplexed LSI pins. Bit: IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 IP13 —...

  • Page 126: Peripheral Function Select Register 14 (Ipsr14)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.22 Peripheral Function Select Register 14 (IPSR14) Function: IPSR14 selects the functions of the multiplexed LSI pins. Bit: IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 IP14 —...

  • Page 127: Peripheral Function Select Register 15 (Ipsr15)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.23 Peripheral Function Select Register 15 (IPSR15) Function: IPSR15 selects the functions of the multiplexed LSI pins. Bit: IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 IP15 — —...

  • Page 128: Peripheral Function Select Register 16 (Ipsr16)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.24 Peripheral Function Select Register 16 (IPSR16) Function: IPSR16 selects the functions of the multiplexed LSI pins. Bit: — — — — — — — — — — — — — — — —...
  • Page 129 RZ/G1H 5. Pin Function Controller (PFC) Table 5.2 Correspondence between Function Signals and Register Bit Settings Peripheral Module (GP Set Value = 1) GPIO/ Function Selected by IP Bits GPIO Peripheral Peripheral (GP Set Function 1 Function 2 Function 3...
  • Page 130 RZ/G1H 5. Pin Function Controller (PFC) Peripheral Module (GP Set Value = 1) GPIO/ Function Selected by IP Bits GPIO Peripheral Peripheral (GP Set Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8...
  • Page 131 RZ/G1H 5. Pin Function Controller (PFC) Peripheral Module (GP Set Value = 1) GPIO/ Function Selected by IP Bits GPIO Peripheral Peripheral (GP Set Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8...
  • Page 132 RZ/G1H 5. Pin Function Controller (PFC) Peripheral Module (GP Set Value = 1) GPIO/ Function Selected by IP Bits GPIO Peripheral Peripheral (GP Set Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8...
  • Page 133 RZ/G1H 5. Pin Function Controller (PFC) Peripheral Module (GP Set Value = 1) GPIO/ Function Selected by IP Bits GPIO Peripheral Peripheral (GP Set Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Function 8...

  • Page 134: Module Select Register (Mod_Sel)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.25 Module Select Register (MOD_SEL) Function: MOD_SEL selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the MSIOF, LBSC, VIN, SRU, and SCIF is assigned to two or more groups of pins.
  • Page 135 RZ/G1H 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4)
  • Page 136 RZ/G1H 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4)
  • Page 137 RZ/G1H 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4)

  • Page 138: Module Select Register 2 (Mod_Sel2)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.26 Module Select Register 2 (MOD_SEL2) Function: MOD_SEL2 selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the SRU, HSCIF, ADCIF, RCAN, SCIF, and TMU is assigned to two or more groups of pins.
  • Page 139 RZ/G1H 5. Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Function 7 Bit Name (Set Value = H'0) (Set Value = H'1) (Set Value = H'2) (Set Value = H'3) (Set Value = H'4)

  • Page 140: Module Select Register 3 (Mod_Sel3)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.27 Module Select Register 3 (MOD_SEL3) Function: MOD_SEL3 selects the group for multiple LSI pins with multiplexed pin functions. Each input or input/output signal of the IIC3 (DVFS), and TMU is assigned to two or more groups of pins. Select one of these groups when using these signals.

  • Page 141: Lsi Pin Pull-Up Control Register 0 (Pupr0)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.28 LSI Pin Pull-Up Control Register 0 (PUPR0) Function: PUPR0 performs on/off control of the pull-up resistors. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

  • Page 142: Lsi Pin Pull-Up Control Register 2 (Pupr2)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.30 LSI Pin Pull-Up Control Register 2 (PUPR2) Function: PUPR2 performs on/off control of the pull-up resistors. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

  • Page 143: Lsi Pin Pull-Up Control Register 4 (Pupr4)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.32 LSI Pin Pull-Up Control Register 4 (PUPR4) Function: PUPR4 performs on/off control of the pull-up resistors. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

  • Page 144: Lsi Pin Pull-Up Control Register 6 (Pupr6)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.34 LSI Pin Pull-Up Control Register 6 (PUPR6) Function: PUPR6 performs on/off control of the pull-up resistors. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

  • Page 145: Iic3 (Dvfs)/Mmc Io Cell Control Register (Ioctrl)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.35 IIC3 (DVFS)/MMC IO Cell Control Register (IOCTRL) Function: IOCTRL controls the driving abilities of pins in use for the IIC3 (DVFS) and MMC interfaces. This register is internal use and reserved; the value of this register should not be changed.

  • Page 146: Sd Control Register 0 (Ioctrl0)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.36 SD Control Register 0 (IOCTRL0) Function: IOCTRL0 controls the driving abilities of pins in use for the SD0 and SD3 interfaces. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 147 RZ/G1H 5. Pin Function Controller (PFC) Initial Bit Name Value Description drv2_sd0d0 SD0_DAT0 Setting: The value of these bits must be 11. drv1_sd0d0 Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately before setting this register.

  • Page 148: Sd Control Register 1 (Ioctrl1)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.37 SD Control Register 1 (IOCTRL1) Function: IOCTRL1 controls the driving abilities of pins in use for the SD1 and SD2 interfaces. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

  • Page 149: Vi1 Driving Ability Control Register (Ioctrl4)

    RZ/G1H 5. Pin Function Controller (PFC) Initial Bit Name Value Description drv2_sd1d0 SD1_DAT0 Setting. The value of these bits must be 11. drv1_sd1d0 Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately before setting this register.

  • Page 150: Tdsel Control Register (Ioctrl5)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.39 TDSEL Control Register (IOCTRL5) Function: IOCTRL5 controls the internal-chip clock delay to be used for data reception. This register is internal use and reserved; the value of this register should not be changed.

  • Page 151: Poc Control Register (Ioctrl6)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.40 POC Control Register (IOCTRL6) Function: IOCTRL6 controls the IO voltage of pins in use for the SD interfaces. Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
  • Page 152 RZ/G1H 5. Pin Function Controller (PFC) Notes: 1. Any pin belongs to the same SD channel must be set to the same IO voltage as VCCQ_SDn. Even though setting different voltage for each pin of the same SD channel, it is impossible to change each pin voltage from the power supply voltage of the VCCQ_SDn.

  • Page 153: Ddr3 General Port Io Enable Register (Ddr3Gpen)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.41 DDR3 General Port IO Enable Register (DDR3GPEN) Function: DDR3GPEN is used to write values to enable DDR3 general port function. Bit: DDR3GPEN[31:16] Initial value: R/W: Bit: DDR3GPEN[15:0] Initial value: R/W: Initial Bit Name...

  • Page 154: Ddr3 General Port Output Enable Register (Ddr3Gpoe)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.42 DDR3 General Port Output Enable Register (DDR3GPOE) Function: DDR3GPOE is use to enable output of DDR3 general port function. Bit: DDR3GPOE[31:16] Initial value: R/W: Bit: DDR3GPOE[15:0] Initial value: R/W: Initial Bit Name Value...
  • Page 155 RZ/G1H 5. Pin Function Controller (PFC) Initial Bit Name Value Description DDR3GPOE[16] Enabling output of DDR3 general port function bit 16 0: Disabled. 1: Enabled. DDR3GPOE[15] Enabling output of DDR3 general port function bit 15 0: Disabled. 1: Enabled. DDR3GPOE[14] —...

  • Page 156: Ddr3 General Port Output Data Register (Ddr3Gpod)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.43 DDR3 General Port Output Data Register (DDR3GPOD) Function: DDR3GPOD is use to write data to DDR3 general port. Bit: DDR3GPOD[31:16] Initial value: R/W: Bit: DDR3GPOD[15:0] Initial value: R/W: Initial Bit Name Value Description DDR3GPOD[31] —...
  • Page 157 RZ/G1H 5. Pin Function Controller (PFC) Initial Bit Name Value Description DDR3GPOD[1] For writing values to DDR3 general port bit 1 DDR3GPOD[0] — Note: To enable this register to be set, appropriately set the multiplexed pin setting mask register (PMMR) immediately before setting this register.

  • Page 158: Ddr3 General Port Input Data Register (Ddr3Gpid)

    RZ/G1H 5. Pin Function Controller (PFC) 5.3.44 DDR3 General Port Input Data Register (DDR3GPID) Function: DDR3GPID is use to read input data from DDR3 general port. Bit: DDR3GPID[31:16] Initial value: R/W: Bit: DDR3GPID[15:0] Initial value: R/W: Bit Name Initial Value...
  • Page 159 RZ/G1H 5. Pin Function Controller (PFC) Bit Name Initial Value Description DDR3GPID[0] — R01UH0627EJ0100 Rev.1.00 5-66 Sep 30,2016...

  • Page 160: Operation

    RZ/G1H 5. Pin Function Controller (PFC) Operation 5.4.1 Function Setting for Multiplexed Pins Setting the LSI multiplexed pin setting mask register (PMMR) is necessary before setting each of the GPIO/peripheral function select registers 0 to 5 (GPSR0 to GPSR5) and peripheral function select registers 0 to 16 (IPSR0 to IPSR16).

  • Page 161: Setting Pull-Up Resistors

    RZ/G1H 5. Pin Function Controller (PFC) Procedure 1 for changing pin function from one peripheral function to another peripheral function Set the LSI multiplexed pin setting mask register Clock (CP φ ) Set the GPIO/peripheral function select register (GP) to GPIO...

  • Page 162: Main Revisions And Additions In This Edition

    Main Revisions and Additions in this Edition Minor revisions such as corrections of errors in spelling and modifications of wording are not included in the revision history. Description Rev. Page Contents Summary 1.00 — First edition issued R01UH0627EJ0100 Rev.1.00 Sep 30,2016...
  • Page 163 RZ/G1H User’s Manual: Hardware Publication Date: Rev.1.00 Sep 30, 2016 Published by: Renesas Electronics Corporation...
  • Page 164 SALES OFFICES SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
  • Page 165 RZ/G1H R01UH0627EJ0100...

Table of Contents