Figure 16. Processor Clock Pulse (Clk2); Figure 17. Reset Signal Timing - Intel 80960MC Manual

HIGH LEVEL (MIN) 0.55V
CC
LOW LEVEL (MAX) 0.8V
CLK2
CLK
RESET
OUTPUTS
INIT PARAMETERS (BADAC,
INT /IAC) MUST BE SET UP 8 CLOCKS
0
PRIOR TO THIS CLK2 EDGE
INIT PARAMETERS MUST BE HELD
BEYOND THIS CLK2 EDGE
21
T
T
3
90%
1.5 V
10%
T
T
5
4

Figure 16. Processor Clock Pulse (CLK2)

...
...
...
T
T
15
T
17
...

Figure 17. RESET Signal Timing

1
T
2
FIRST
A B C D A
16
T = RESET HOLD
15
T = RESET SETUP
16
T = RESET WIDTH
17
80960MC