Unused Channel B; Single Channel 2-Dimm Implementation; Single Channel 4-Dimm Implementation - Intel Xeon Design Manual

Intel
Single Channel routing guidelines listed in the following sections are described for one or two
DIMMs. When single channel three or four DIMMs guidelines are needed, follow the dual channel
guidelines for three or four DIMMs listed in
Figure 14. Single Channel 2-DIMM Implementation
Figure 15. Single Channel 4-DIMM Implementation
3.3.1

Unused Channel B

Channel B is not used in a single-channel configuration. Therefore, Channel B's associated signals
should terminate as described in
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
MCH
MCH
SMBus Address:
Command Clock:
Chip Select:
Table
®
E7500/E7501 Chipset Compatible Platform
Section 3.2, "Dual Channel DDR
D
I
M
M
A1
SMBus Address: 00h
Command Clock: 0/0#
Chip Select: 0/1
D D
I I
M M
M M
A1 A2 A3
00h 01h 02h
0/0# 1/1# 2/2#
0/1 2/3 4/5
13.
Overview".
Fill First
D
I
M
M
A2
01h
1/1#
2/3
Fill First
D D
I I
M M
M M
A4
03h
3/3#
6/7
31