With Rgmii; Multiple Cores; With External Gmii; Figure 10-2: Clock Management With External Rgmii - Xilinx LogiCORE IP MAC v8.5 User Manual

R

With RGMII

Standard Clocking Scheme
Figure 10-2
clocks illustrated have a frequency of 125 MHz. The gtx_clk clock must be provided to
the GEMAC core. This is a high-quality clock that satisfies IEEE 802.3-2005 requirements. It
is expected that this clock will be derived from an external oscillator and connected into the
device through an IBUFG as illustrated in
to a DCM from where phase-shifted clock signals are generated for use in the RGMII
transmitter logic. The zero phase-shifted clock is used as the input gtx_clk to the
GEMAC core.
The receiver clock, rgmii_rxc is usually derived from a different clock source to
gtx_clk. In this case, rgmii_rxc will be received through an IBUFG. This clock is routed
into a DCM where it is used to generate phase-shifted clock signals for use in the RGMII
receiver logic. A fixed phase-shift value is applied to the DCM to meet RGMII setup and
hold requirements. See
used as the input gmii_rx_clk to the GEMAC core.
gtx_clk

Multiple Cores

With External GMII

Figure 10-3
core when using the optional GMII. gtx_clk may be shared between multiple cores as
illustrated, resulting in a common transmitter clock domain across the device.
A common receiver clock domain is usually not possible as each core will receive an
independent receiver clock from the PHY attached to the other end of the GMII. As
illustrated in
110
-- DISCONTINUED PRODUCT --
illustrates the clock management used with an external RGMII interface. All
Appendix C, "Calculating DCM Phase-Shifting."
BUFG
DCM
CLK_0
IBUFG
BUFG
CLK_90
RGMII Tx Logic

Figure 10-2: Clock Management with External RGMII

illustrates how to share clock resources across multiple instantiations of the
Figure 10-3, this results in a separate receiver clock domain for each core.
www.xilinx.com
Chapter 10: Clocking and Resetting
Figure 10-2. This clock is used as the input clock
1-Gigabit Ethernet
MAC Core
BUFG
gtx_clk gmii_rx_clk
RGMII Rx Logic
1-Gigabit Ethernet MAC v8.5 User Guide
The zero clock is
DCM
CLK_0
IBUFG
rgmii_rxc
UG144 April 24, 2009