ST STM32L4 5 Series Reference Manual page 1611

RM0351
CAN receive FIFO mailbox data low register (CAN_RDLxR) (x = 0..1)
All bits of this register are write protected when the mailbox is not in empty state.
Address offsets: 0x1B8, 0x1C8
Reset value: 0xXXXX XXXX
All RX registers are write protected.
31 30 29
r r r
15 14 13
r r r
Bits 31:24 DATA3[7:0]
Bits 23:16 DATA2[7:0]
Bits 15:8 DATA1[7:0]
Bits 7:0 DATA0[7:0]
CAN receive FIFO mailbox data high register (CAN_RDHxR) (x = 0..1)
Address offsets: 0x1BC, 0x1CC
Reset value: 0xXXXX XXXX
All RX registers are write protected.
31 30 29
r r r
15 14 13
r r r
Bits 31:24 DATA7[7:0]
Data byte 3 of the message.
28 27 26 25
DATA3[7:0]
r r r r
12 11 10 9
DATA1[7:0]
r r r r
:
Data Byte 3
Data byte 3 of the message.
:
Data Byte 2
Data byte 2 of the message.
:
Data Byte 1
Data byte 1 of the message.
:
Data Byte 0
Data byte 0 of the message.
A message can contain from 0 to 8 data bytes and starts with byte 0.
28 27 26 25
DATA7[7:0]
r r r r
12 11 10 9
DATA5[7:0]
r r r r
:
Data Byte 7
DocID024597 Rev 5
Controller area network (bxCAN)
24 23 22 21
r r r r
8 7 6 5
r r r r
24 23 22 21
r r r r
8 7 6 5
r r r r
20 19 18 17
DATA2[7:0]
r r r r
4 3 2 1
DATA0[7:0]
r r r r
20 19 18 17
DATA6[7:0]
r r r r
4 3 2 1
DATA4[7:0]
r r r r
1611/1830
16
r
0
r
16
r
0
r