Epson S1C17624 Technical Manual page 235

22 iR ReMOTe COnTROlleR (ReMC)
The carrier generation clock is generated by dividing PCLK into 1/1 to 1/16K. The division ratio can be selected
from the 15 types shown below using CGCLK[3:0]/REMC_CFG register.
Table 22.
CGClK[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
notes: • The clock generator (CLG) must be configured to supply PCLK to the peripheral modules be-
fore running the REMC.
• Make sure the REMC is halted before setting the clock.
For detailed information on the CLG control, see the "Clock Generator (CLG)" chapter.
The carrier H and L section lengths are set by REMCH[5:0]/REMC_CAR register and REMCL[5:0]/REMC_CAR
register, respectively. Set a value corresponding to the number of clock (selected as above) cycles + 1 to these regis-
ters.
The carrier H and L section lengths can be calculated as follows:
Carrier H section length = —————— [s]
Carrier L section length = —————— [s]
REMCH: Carrier H section length data value
REMCL: Carrier L section length data value
cg_clk: Carrier generation clock frequency
The carrier signal is generated from these settings as shown in Figure 22.3.1.
Example: CGCLK[3:0] = 0x2 (PCLK/4), REMCH[5:0] = 2, REMCL[5:0] = 1
Carrier generation clock
22.4 Data length Counter Clock Settings
The data length counter is an 8-bit counter for setting data lengths when transmitting data.
When a value corresponding to the data pulse width is written during data transmission, the data length counter
begins counting down from that value and stops after generating an underflow interrupt cause when the counter
reaches 0. The subsequent transmit data is set using this interrupt.
This counter is also used for data receiving, enabling measurement of the received data length. Interrupts can be
generated at the input signal rising or falling edges when receiving data. The data pulse length can be obtained from
the difference between data pulse edges by setting the data length counter to 0xff using the interrupt when the input
changes and by reading out the count value when a subsequent interrupt occurs due to input changes.
22-2
3.1 Carrier Generation Clock (PCLK Division Ratio) Selection
Division ratio
Reserved
1/16384
1/8192
1/4096
1/2048
1/1024
1/512
1/256
REMCH + 1
cg_clk
REMCL + 1
cg_clk
PCLK
0
Count
Carrier
Carrier H section length
Figure 22. 3.1 Carrier Signal Generation
Seiko epson Corporation
CGClK[3:0]
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
1 2 0
Carrier L section length
S1C17624/604/622/602/621 TeChniCal Manual
Division ratio
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
(Default: 0x0)
1 0