Epson S1C17624 Technical Manual page 69

7 ClOCK GeneRaTOR (ClG)
7.8 ReSeT and nMi input noise Filters
Since accidental activation of RESET or NMI by noise in the external input signals will cause unintended resetting
or NMI processing, the CLG module incorporates noise filters operated by the system clock (SYSCLK). The filters
remove noise from these signals before they reach the S1C17 Core or peripheral modules. Separate noise filters are
used for each signal. You can select to use or bypass them individually.
RESET input noise filter: Filters noise when RSTFE/OSC_NFEN register = 1; bypassed when RSTFE = 0
NMI input noise filter:
notes: • The RESET input noise filter should normally be enabled.
• The S1C17624/604/622/602/621 has no external NMI input pin, but the watchdog timer NMI
request signal passes through the filter.
7.9 Control Register Details
address
0x4020 PSC_CTL Prescaler Control Register
0x5060 OSC_SRC Clock Source Select Register
0x5061 OSC_CTL Oscillation Control Register
0x5062 OSC_NFEN Noise Filter Enable Register
0x5064 OSC_FOUT FOUT Control Register
0x5080 CLG_PCLK PCLK Control Register
0x5081 CLG_CCLK CCLK Control Register
The CLG module registers are described in detail below. These are 8-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
Prescaler Control Register (PSC_CTl)
Register name address Bit
Prescaler 0x4020 D7–2 –
Control Register
(8 bits)
D1
(PSC_CTl)
D0
D[7:2] Reserved
D1 PRunD: Run/Stop Select Bit in Debug Mode
Selects the operating status of the peripheral circuits that operate with PCLK in debug mode.
1 (R/W): Run
0 (R/W): Stop (default)
Setting PRUND to 1 enables the peripheral circuits that operate with PCLK to run even in debug mode.
Setting it to 0 will stop them when the S1C17 Core enters debug mode. Set PRUND to 1 to maintain
running status for these peripheral circuits in debug mode.
D0 PRun: Prescaler Run/Stop Control Bit
Starts or stops prescaler operation.
1 (R/W): Start operation
0 (R/W): Stop (default)
Write 1 to PRUN to operate the prescalers for peripheral modules. Write 0 to PRUN to stop the prescalers.
Clock Source Select Register (OSC_SRC)
Register name address Bit
Clock Source 0x5060 D7–2 –
Select Register
(8 bits)
D1
(OSC_SRC)
D0
D[7:2] Reserved
7-10
Filters noise when NMIFE/OSC_NFEN register = 1; bypassed when NMIFE = 0
Table 7. 9.1 List of CLG Registers
Register name
name Function
reserved
PRunD
Run/stop select in debug mode
PRun Prescaler run/stop control
name Function
reserved
hSClKSel High-speed clock select
ClKSRC
System clock source select
Seiko epson Corporation
Function
Controls prescalers.
Selects the clock source.
Controls oscillation.
Enables/disables noise filters.
Controls FOUTH/FOUT1 clock outputs.
Controls the PCLK supply.
Configures the CCLK division ratio.
Setting
–
1 Run 0 Stop
1 Run 0 Stop
Setting
–
1 OSC3 0 IOSC
1 OSC1 0 HSCLK
S1C17624/604/622/602/621 TeChniCal Manual
init. R/W Remarks
– – 0 when being read.
0 R/W
0 R/W
init. R/W Remarks
– – 0 when being read.
0 R/W
0 R/W