Epson S1C17624 Technical Manual page 205

SPTBE is set to 0 when transmit data is written to the SPI_TXDx register (transmit data buffer), and is
set to 1 when the data is transferred to the shift register (when transmission starts).
Transmission data must be written to the SPI_TXDx register when this bit is 1.
SPi Ch.x Transmit Data Register (SPi_TXDx)
Register name address Bit
SPi Ch.x 0x4322 D15–8 –
Transmit Data
(16 bits) D7–0 SPTDB[7:0] SPI transmit data buffer
Register
(SPi_TXDx)
D[15:8] Reserved
D[7:0] SPTDB[7:0]: SPi Transmit Data Buffer Bits
Sets transmit data to be written to the transmit data buffer. (Default: 0x0)
In master mode, transmission is started by writing data to this register. In slave mode, the contents of
this register are sent to the shift register and transmission begins when the clock is input from the mas-
ter.
SPTBE/SPI_STx register is set to 1 (empty) as soon as data written to this register has been transferred
to the shift register. A transmit buffer empty interrupt is generated at the same time. The subsequent
transmit data can then be written, even while data is being transmitted.
Serial converted data is output from the SDOx pin, with the bit set to 1 as High level and the bit set to 0
as Low level.
note: Make sure that SPEN is set to 1 before writing data to the SPI_TXDx register to start data trans-
mission/reception.
SPi Ch.x Receive Data Register (SPi_RXDx)
Register name address Bit
SPi Ch.x 0x4324 D15–8 –
Receive Data
(16 bits) D7–0 SPRDB[7:0] SPI receive data buffer
Register
(SPi_RXDx)
D[15:8] Reserved
D[7:0] SPRDB[7:0]: SPi Receive Data Buffer Bits
Contains the received data. (Default: 0x0)
SPRBF/SPI_STx register is set to 1 (data full) as soon as data is received and the shift register data has
been transferred to the receive data buffer. A receive buffer full interrupt is generated at the same time.
Data can then be read until subsequent data is received. If receiving the subsequent data is completed
before the register has been read out, the new received data overwrites the contents.
Serial data input from the SDIx pin is converted to parallel, with the High level bit set to 1 and the Low
level bit set to 0. The data is the loaded into this register.
This register is read-only.
SPi Ch.x Control Register (SPi_CTlx)
Register name address Bit
SPi Ch.x Con- 0x4326 D15–10 –
trol Register (16 bits)
D9
(SPi_CTlx)
D8
D7–6 –
D5
D4
D3
D2
D1
D0
note: In the S1C17602/621, do not access to the SPI_CTLx register while SPBSY/SPI_STx register is
set to 1 or SPRBF/SPI_STx register is set to 1 (while data is being transmitted/received).
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
SPTDB7 = MSB
SPTDB0 = LSB
name Function
reserved
SPRDB7 = MSB
SPRDB0 = LSB
name Function
reserved
MClK SPI clock source select
MlSB
LSB/MSB first mode select
reserved
SPRie
Receive data buffer full int. enable 1 Enable
SPTie Transmit data buffer empty int. enable 1 Enable
CPha
Clock phase select
CPOl
Clock polarity select
MSSl
Master/slave mode select
SPen
SPI enable
Seiko epson Corporation
Setting init. R/W
–
0x0 to 0xff 0x0 R/W
Setting init. R/W
–
0x0 to 0xff 0x0
Setting init. R/W
–
1 T16 Ch.1 0 PCLK/4
1 LSB 0 MSB
–
0 Disable
0 Disable
1 Data out 0 Data in
1 Active L 0 Active H
1 Master 0 Slave
1 Enable 0 Disable
19 SPi
Remarks
– – 0 when being read.
Remarks
– – 0 when being read.
R
Remarks
– – 0 when being read.
0 R/W
0 R/W
– – 0 when being read.
0 R/W
0 R/W
0 R/W These bits must be
set before setting
0 R/W
SPEN to 1.
0 R/W
0 R/W
19-7