Table of Contents
Advertisement
aPPenDiX a liST OF i/O ReGiSTeRS
Register name address
Bit
P4 Port Pull-up
0x5243
D7–0 P4Pu[7:0]
Control Register
(8 bits)
(P4_Pu)
P4 Port Schmitt
0x5244
D7–4 P4SM[7:4]
Trigger Control
(8 bits)
Register
D3–0 P4SM[3:0]
(P4_SM)
P4 Port input
0x524a
D7–0 P4ien[7:0] P4[7:0] port input enable
enable Register
(8 bits)
(P4_ien)
P5 Port input
0x5250
D7
Data Register
(8 bits)
D6–0 P5in[6:0]
(P5_in)
(S1C17624/622)
0x5251
P5 Port Output
D7
Data Register
(8 bits)
D6–0 P5OuT[6:0] P5[6:0] port output data
(P5_OuT)
(S1C17624/622)
P5 Port
0x5252
D7
Output enable
(8 bits)
D6–0 P5Oen[6:0] P5[6:0] port output enable
Register
(P5_Oen)
(S1C17624/622)
P5 Port Pull-up
0x5253
D7
Control Register
(8 bits)
D6–0 P5Pu[6:0]
(P5_Pu)
(S1C17624/622)
P5 Port Schmitt
0x5254
D7
Trigger Control
(8 bits)
D6–3 P5SM[6:3]
Register
(P5_SM)
D2–0 P5SM[2:0]
(S1C17624/622)
P5 Port input
0x525a
D7
enable Register
(8 bits)
D6–0 P5ien[6:0] P5[6:0] port input enable
(P5_ien)
(S1C17624/622)
P0[3:0] Port
0x52a0
D7–6 P03MuX[1:0] P03 port function select
Function Select
(8 bits)
Register
(P00_03PMuX)
D5–4 P02MuX[1:0] P02 port function select
D3–2 P01MuX[1:0] P01 port function select
D1–0 P00MuX[1:0] P00 port function select
P0[7:4] Port
0x52a1
D7–6 P07MuX[1:0] P07 port function select
Function Select
(8 bits)
Register
(P04_07PMuX)
D5–4 P06MuX[1:0] P06 port function select
D3–2 P05MuX[1:0] P05 port function select
D1–0 P04MuX[1:0] P04 port function select
aP-a-18
name
Function
P4[7:0] port pull-up enable
P4[7:4] port Schmitt trigger input
enable
P4[3:0] port Schmitt trigger input
enable
–
reserved
P5[6:0] port input data
–
reserved
–
reserved
–
reserved
P5[6:0] port pull-up enable
–
reserved
P5[6:3] port Schmitt trigger input
enable
P5[2:0] port Schmitt trigger input
enable
–
reserved
Seiko epson Corporation
Setting
init. R/W
1 Enable
0 Disable
(0xff)
1 Enable
0 Disable
(Schmitt)
(CMOS)
1 Enable
0 –
(Schmitt)
1 Enable
0 Disable
(0xff)
–
1 1 (H)
0 0 (L)
–
1 1 (H)
0 0 (L)
–
1 Enable
0 Disable
–
1 Enable
0 Disable
(0x7f)
–
1 Enable
0 –
(Schmitt)
1 Enable
0 Disable
(Schmitt)
(CMOS)
–
1 Enable
0 Disable
(0x7f)
P03MUX[1:0]
Function
0x0 R/W
0x3
reserved
0x2
reserved
0x1
#ADTRG
0x0
P03
P02MUX[1:0]
Function
0x0 R/W
0x3
reserved
0x2
reserved
0x1
reserved
0x0
P02/EXCL0
P01MUX[1:0]
Function
0x0 R/W
0x3
reserved
0x2
reserved
0x1
REMI
0x0
P01
P00MUX[1:0]
Function
0x0 R/W
0x3
reserved
0x2
reserved
0x1
REMO
0x0
P00
P07MUX[1:0]
Function
0x0 R/W
0x3
reserved
0x2
reserved
0x1
#SPISS0
0x0
P07
P06MUX[1:0]
Function
0x0 R/W
0x3
reserved
0x2
reserved
0x1
SDI0
0x0
P06
P05MUX[1:0]
Function
0x0 R/W
0x3
reserved
0x2
reserved
0x1
SDO0
0x0
P05
P04MUX[1:0]
Function
0x0 R/W
0x3
reserved
0x2
reserved
0x1
SPICLK0
0x0
P04
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
1
R/W D[7:4] =reserved in
S1C17604/602/621
1
R/W D[7:4] = reserved in
S1C17604/602/621
1
R
Always enabled
1
R/W D[7:4] =reserved in
S1C17604/602/621
–
–
0 when being read.
×
R
–
–
0 when being read.
0
R/W
–
–
0 when being read.
0
R/W
–
–
0 when being read.
1
R/W
–
–
0 when being read.
1
R
Always enabled
1
R/W
–
–
0 when being read.
1
R/W
Advertisement
Table of Contents
