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27
On-chip Debugger (DBG)
27.1
Resource Requirements and Debugging Tools
Debugging work area
Debugging requires a 64-byte debugging work area. For more information on the work area location, see the
"Memory Map" chapter.
The start address for this debugging work area can be read from the DBRAM register (0xffff90).
Debugging tools
Debugging involves connecting ICDmini (S5U1C17001H) to the S1C17624/604/622/602/621 debug pins and
inputting the debug instruction from the debugger on the personal computer.
The following tools are required:
• S1C17 Family In-Circuit Debugger ICDmini (S5U1C17001H)
• S1C17 Family C compiler package (e.g., S5U1C17001C)
Debug pins
The following debug pins are used to connect ICDmini (S5U1C17001H).
Pin name
i/O
DCLK
DSIO
I/O
DST2
The on-chip debugger input/output pins (DCLK, DST2, DSIO) are shared with I/O ports and are initially set as
the debug pins. If the debugging function is not used, these pins can be switched using the port function select
bits to enable use as general-purpose I/O port pins.
For detailed information on pin function switching, see the "I/O Ports (P)" chapter.
27.2
Debug Break Operation Status
The S1C17 Core enters debug mode when the brk instruction is executed or a debug interrupt is generated by a
break signal (Low) input to the DSIO pin. This state persists until the retd instruction is executed. During this time,
hardware interrupts and NMIs are disabled.
The default setting halts peripheral circuit operations. This setting can be modified even when debugging is under-
way.
The peripheral circuits that operate with PCLK will continue running in debug mode by setting PRUND/PSC_CTL
register to 1. Setting PRUND to 0 (default) will stop these peripheral circuits in debug mode.
The peripheral circuits that operate with a clock other than PCLK will continue running in debug mode by setting
O1DBG/MISC_OSC1 register to 1. Setting O1DBG to 0 (default) will stop these peripheral circuits in debug mode.
Some peripheral circuits, such as SPI, I2CS, and T16A2, that run with an external input clock will not stop operat-
ing even if the S1C17 Core enters debug mode.
The LCD driver continues the operating status at occurrence of the debug interrupt.
S1C17624/604/622/602/621 TeChniCal Manual
Table 27.
1.1 List of Debug Pins
Qty
O
1
On-chip debugger clock output pin
Outputs a clock to the ICDmini (S5U1C17001H).
1
On-chip debugger data input/output pin
Used to input/output debugging data and input the break signal.
O
1
On-chip debugger status signal output pin
Outputs the processor status during debugging.
Seiko epson Corporation
27 On-ChiP DeBuGGeR (DBG)
Function
27-1
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