Epson S1C17624 Technical Manual page 303

Mode setting
instruction
value
0x07
ld.ca %rd,%rs
(ext
imm9)
ld.ca %rd,imm7
0x17 ld.ca %rd,%rs
(ext
imm9)
ld.ca %rd,imm7
Example:
ld.cw %r0,0x7
ld.ca %r0,%r1
ld.cw %r0,0x13 ; Sets the modes (operation result read mode and 16 high-order bits output mode).
ld.ca %r1,%r0
Conditions to set the overflow (V) flag
An overflow occurs in a MAC operation and the overflow (V) flag is set to 1 when the signs of the multiplica-
tion result, operation result register value, and multiplication & accumulation result match the following condi-
tions:
Mode setting value
0x07
0x07
An overflow occurs when a MAC operation performs addition of positive values and a negative value results, or
it performs addition of negative values and a positive value results. The coprocessor holds the operation result
when the overflow (V) flag is cleared.
Conditions to clear the overflow (V) flag
The overflow (V) flag that has been set will be cleared when an overflow has not been occurred during execu-
tion of the "ld.ca" instruction for MAC operation or when the "ld.ca" or "ld.cf" instruction is executed
in an operation mode other than operation result read mode.
S1C17624/604/622/602/621 TeChniCal Manual
Argument 2
Argument 1
S1C17 Core
Coprocessor
output (16 bits)
Flag output
Figure 28. 5.2 Data Path in MAC Mode
Table 28. 5.2 Operation in MAC Mode
Operations
res[31:0] ← %rd × %rs + res[31:0]
%rd ← res[15:0]
res[31:0] ← %rd × imm7/16 + res[31:0]
%rd ← res[15:0]
res[31:0] ← %rd × %rs + res[31:0]
%rd ← res[31:16]
res[31:0] ← %rd × imm7/16 + res[31:0]
%rd ← res[31:16]
; Sets the modes (signed MAC mode and 16 low-order bits output mode).
; Performs "res = %r0 × %r1 + res" and loads the 16 low-order bits of the result to %r0.
; Loads the 16 high-order bits of the result to %r1.
Table 28. 5.3 Conditions to Set the Overflow (V) Flag
Sign of multiplication result
0 (positive)
1 (negative)
Seiko epson Corporation
28 MulTiPlieR/DiViDeR (COPRO)
16 bits 32 bits
32 bits
Operation
result
Operation result
register
Selector
Flags
psr (CVZN) ← 0b0100
if an overflow has oc-
curred
Otherwise
psr (CVZN) ← 0b0000
Sign of operation result
register value
0 (positive)
1 (negative)
Remarks
The operation result
register keeps the
operation result un-
til it is rewritten by
other operation.
res: operation result register
Sign of multiplication & ac-
cumulation result
1 (negative)
0 (positive)
28-5