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26 SuPPlY VOlTaGe DeTeCTOR (SVD)
D0
SVDen: SVD enable Bit
Enables or disables SVD operations.
1 (R/W): Enabled
0 (R/W): Disabled(default )
Setting SVDEN to 1 initiates power supply voltage detection; setting to 0 stops detection.
notes: • An SVD circuit-enable response time is required to obtain stable detection results after
SVDEN is altered from 0 to 1. Also when SVDC[3:0] is altered, an SVD circuit response
time is required to obtain stable detection results. For these response times, see "Electrical
Characteristics."
• Operating the SVD circuit increases current consumption. If power supply voltage detection
is not required, stop SVD operations by setting SVDEN to 0.
SVD Comparison Voltage Register (SVD_CMP)
Register name address
Bit
SVD
0x5101
D7–4 –
Comparison
(8 bits)
D3–0 SVDC[3:0]
Voltage Register
(SVD_CMP)
D[7:4]
Reserved
D[3:0]
SVDC[3:0]: SVD Comparison Voltage Select Bits
Selects one of 15 comparison voltages for detecting voltage drops.
The SVD circuit compares the power supply voltage (V
SVDC[3:0], and outputs results indicating whether the power supply voltage exceeds this comparison
voltage.
26-4
name
Function
reserved
SVD comparison voltage select
Table 26.
6.2 Comparison Voltage Settings
SVDC[3:0]
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Seiko epson Corporation
Setting
init. R/W
–
–
SVDC[3:0]
Voltage
0x0 R/W
0xf
3.2 V
0xe
3.1 V
0xd
3.0 V
0xc
2.9 V
0xb
2.8 V
0xa
2.7 V
0x9
2.6 V
0x8
2.5 V
0x7
2.4 V
0x6
2.3 V
0x5
2.2 V
0x4
2.1 V
0x3
2.0 V
0x2
1.9 V
0x1
1.8 V
0x0
reserved
Comparison voltage
3.2 V
3.1 V
3.0 V
2.9 V
2.8 V
2.7 V
2.6 V
2.5 V
2.4 V
2.3 V
2.2 V
2.1 V
2.0 V
1.9 V
1.8 V
Reserved
(Default: 0x0)
) against the comparison voltage set by
DD
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
–
0 when being read.
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