Epson S1C17624 Technical Manual page 331

0x4280–0x4288
Register name address Bit
T8F Ch.1 0x4280 D15–4 –
Count Clock
(16 bits) D3–0 DF[3:0]
Select Register
(T8F_ClK1)
T8F Ch.1 0x4282 D15–8 –
Reload Data (16 bits)
D7–0 TR[7:0]
Register
(T8F_TR1)
T8F Ch.1 0x4284 D15–8 –
Counter Data
(16 bits) D7–0 TC[7:0]
Register
(T8F_TC1)
T8F Ch.1 0x4286 D15–12 –
Control Register
(16 bits) D11–8 TFMD[3:0]
(T8F_CTl1)
D7–5 –
D4
D3–2 –
D1
D0
T8F Ch.1 0x4288 D15–9 –
interrupt
(16 bits)
D8
Control Register
D7–1 –
(T8F_inT1)
D0
0x4306–0x4318
Register name address Bit
interrupt level 0x4306 D15–11 –
Setup Register 0 (16 bits)
D10–8 ilV1[2:0]
(iTC_lV0)
D7–3 –
D2–0 ilV0[2:0]
interrupt level 0x4308 D15–11 –
Setup Register 1
(16 bits) D10–8 ilV3[2:0]
(iTC_lV1)
D7–3 –
D2–0 ilV2[2:0]
interrupt level 0x430a D15–11 –
Setup Register 2
(16 bits) D10–8 ilV5[2:0]
(iTC_lV2)
D7–3 –
D2–0 ilV4[2:0]
interrupt level 0x430c D15–11 –
Setup Register 3
(16 bits) D10–8 ilV7[2:0]
(iTC_lV3)
D7–3 –
D2–0 ilV6[2:0]
interrupt level 0x430e D15–11 –
Setup Register 4
(16 bits) D10–8 ilV9[2:0]
(iTC_lV4)
D7–3 –
D2–0 ilV8[2:0]
interrupt level 0x4310 D15–11 –
Setup Register 5
(16 bits) D10–8 ilV11[2:0]
(iTC_lV5)
D7–3 –
D2–0 ilV10[2:0]
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
Count clock division ratio select
reserved
Reload data
TR7 = MSB
TR0 = LSB
reserved
Counter data
TC7 = MSB
TC0 = LSB
reserved
Fine mode setup
reserved
TRMD Count mode select
reserved
PReSeR Timer reset
PRun Timer run/stop control
reserved
T8Fie
T8F interrupt enable
reserved
T8FiF
T8F interrupt flag
name Function
reserved
P1 interrupt level
reserved
P0 interrupt level
reserved
CT/RTC interrupt level
reserved
SWT interrupt level
reserved
SVD interrupt level
reserved
T8OSC1 interrupt level
reserved
T16E Ch.0 interrupt level
reserved
LCD/T16A2 Ch.0 interrupt level
reserved
T16 Ch.0 interrupt level
reserved
T8F Ch.0/Ch.1 interrupt level
reserved
T16 Ch.2 interrupt level
reserved
T16 Ch.1 interrupt level
Seiko epson Corporation
aPPenDiX a liST OF i/O ReGiSTeRS
Fine Mode 8-bit Timer Ch.1
Setting init. R/W
–
DF[3:0] Division ratio 0x0 R/W Source clock = PCLK
0xf reserved
0xe 1/16384
0xd 1/8192
0xc
1/4096
0xb 1/2048
0xa 1/1024
0x9 1/512
0x8 1/256
0x7 1/128
0x6 1/64
0x5 1/32
0x4 1/16
0x3 1/8
0x2 1/4
0x1 1/2
0x0 1/1
–
0x0 to 0xff 0x0 R/W
–
0x0 to 0xff 0xff
–
0x0 to 0xf 0x0 R/W Set a number of times
–
1 One shot 0 Repeat
–
1 Reset 0 Ignored
1 Run 0 Stop
–
1 Enable 0 Disable
–
1 Cause of 0 Cause of
interrupt interrupt not
occurred occurred
interrupt Controller
Setting init. R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
–
0 to 7 0x0 R/W
Remarks
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
R
– – 0 when being read.
to insert delay into a
16-underflow period.
– – 0 when being read.
0 R/W
– – 0 when being read.
0 W
0 R/W
– – 0 when being read.
0 R/W
– – 0 when being read.
0 R/W Reset by writing 1.
Remarks
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
– – 0 when being read.
aP-a-9