Epson S1C17624 Technical Manual page 147

13 16-BiT PWM TiMeRS (T16a2)
Clock enable
Clock supply to the counter is controlled using CLKEN/T16A_CLKx register. The CLKEN default setting is
0, which disables the clock supply. Setting CLKEN to 1 sends the clock generated as above to the counter. If
T16A2 is not required, disable the clock supply to reduce current consumption.
Multi-comparator/capture mode
The T16A2 module allows a counter channel to be connected to multiple comparator/capture channels (multi-
comparator/capture mode). In this case, all channels must be clocked with the Ch.0 clock. Use MULTIMD/
T16A_CLK0 register to supply the Ch.0 clock to all channels. When using T16A2 in multi-comparator/capture
mode, set MULTIMD to 1. When connecting the counter and comparator/capture block in the same channel
(normal channel mode), set MULTIMD to 0 (default).
note: Make sure the T16A2 count is stopped before setting the count clock.
13.4 T16a2 Operating Modes
The T16A2 module provides some operating modes to support various usages. This section describes the functions
of each operating mode and how to enter the mode.
13.4.1 Comparator Mode and Capture Mode
The T16A_CCAx and T16A_CCBx registers that are embedded in the comparator/capture block can be set to com-
parator mode or capture mode, individually. The T16A_CCAx register mode is selected using CCAMD/T16A_
CCCTLx register and the T16A_CCBx register mode is selected using CCBMD/T16A_CCCTLx register.
Comparator mode (CCaMD/CCBMD = 0, default)
The comparator mode compares the counter value and the comparison value set via software. It generates an
interrupt and toggles the timer output signal level when the values are matched. The T16A_CCAx and T16A_
CCBx registers function as the compare A and compare B registers that are used for loading compare values in
this mode.
When the counter reaches the value set in the compare A register during counting, the comparator asserts the
compare A signal. At the same time the compare A interrupt flag is set and the interrupt signal of the timer
channel is output to the ITC if the interrupt has been enabled.
When the counter reaches the value set in the compare B register, the comparator asserts the compare B signal.
At the same time the compare B interrupt flag is set and the interrupt signal of the timer channel is output to the
ITC if the interrupt is enabled. Furthermore, the counter is reset to 0.
The compare A period (time from start of counting to occurrence of a compare A interrupt) and the compare B
period (time from start of counting to occurrence of a compare B interrupt) can be calculated as follows:
Compare A period = (CCA + 1) / ct_clk [second]
Compare B period = (CCB + 1) / ct_clk [second]
CCA: Compare A register value set (0 to 65535)
CCB: Compare B register value set (0 to 65535)
ct_clk: Count clock frequency [Hz]
The compare A and compare B signals are also used to generate a timer output waveform (TOUT). See Section
13.6, "Timer Output Control," for more information.
To generate PWM waveform, the T16A_CCAx and T16A_CCBx registers must be both placed into comparator
mode.
Compare buffers
The compare buffer is used to synchronize the comparison data update timings and the counter operation.
Setting CBUFEN/T16A_CTLx register to 1 enables the compare buffer. The compare A and B signals will
be generated by comparing the counter values with the compare A and B buffer values instead of the com-
pare A and B register values. The compare A and B register values written via software are loaded to the
compare A and B buffers when the compare B signal is generated.
13-4
Seiko epson Corporation
S1C17624/604/622/602/621 TeChniCal Manual