Epson S1C17624 Technical Manual page 294

27 On-ChiP DeBuGGeR (DBG)
27.3 additional Debugging Function
The S1C17624/604/622/602/621 expands the following on-chip debugging functions of the S1C17 Core.
Branching destination in debug mode
When a debug interrupt is generated, the S1C17 Core enters debug mode and branches to the debug processing
routine. In this process, the S1C17 Core is designed to branch to address 0xfffc00. In addition to this branching
destination, the S1C17624/604/622/602/621 also allows designation of address 0x0 (beginning address of the
internal RAM) as the branching destination when debug mode is activated. The branching destination address is
selected using DBADR/MISC_IRAMSZ register. When the DBADR is set to 0 (default), the branching destina-
tion is set to 0xfffc00. When it is set to 1, the branching destination is set to 0x0.
adding instruction breaks
The S1C17 Core supports two instruction breaks (hardware PC breaks). The S1C17624/604/622/602/621 in-
creased this number to five, adding the control bits and registers given below.
• IBE2/DCR register:
• IBE3/DCR register:
• IBE4/DCR register:
• IBAR2[23:0]/IBAR2 register: Set instruction break address #2.
• IBAR3[23:0]/IBAR3 register: Set instruction break address #3.
• IBAR4[23:0]/IBAR4 register: Set instruction break address #4.
Note that the debugger included in the S5U1C17001C (Ver. 1.2.1) or later is required to use five hardware PC
breaks.
27.4 Control Register Details
address
0x4020 PSC_CTL Prescaler Control Register
0x5322 MISC_OSC1 OSC1 Peripheral Control Register
0x5326 MISC_IRAMSZ IRAM Size Select Register
0xffff90 DBRAM Debug RAM Base Register
0xffffa0 DCR Debug Control Register
0xffffb8 IBAR2 Instruction Break Address Register 2
0xffffbc IBAR3 Instruction Break Address Register 3
0xffffd0 IBAR4 Instruction Break Address Register 4
The debug registers are described in detail below.
notes: • When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
• For debug registers not described here, refer to the S1C17 Core Manual.
Prescaler Control Register (PSC_CTl)
Register name address Bit
Prescaler 0x4020 D7–2 –
Control Register
(8 bits)
D1
(PSC_CTl)
D0
D[7:2] Reserved
D1 PRunD: Run/Stop Select Bit in Debug Mode
Selects the operating status of the peripheral circuits that operate with PCLK in debug mode.
1 (R/W): Run
0 (R/W): Stop (default)
27-2
Enables instruction breaks #2.
Enables instruction breaks #3.
Enables instruction breaks #4.
Table 27. 4.1 List of Debug Registers
Register name
name Function
reserved
PRunD
Run/stop select in debug mode
PRun
Prescaler run/stop control
Seiko epson Corporation
Function
Controls prescalers.
Enables peripheral operations in debug mode (except PCLK).
Selects the IRAM size.
Indicates the debug RAM base address.
Controls debugging.
Sets Instruction break address #2.
Sets Instruction break address #3.
Sets Instruction break address #4.
Setting
–
1 Run 0 Stop
1 Run 0 Stop
S1C17624/604/622/602/621 TeChniCal Manual
init. R/W Remarks
– – 0 when being read.
0 R/W
0 R/W