Epson S1C17624 Technical Manual page 51

5 Initial Reset
5.1 initial Reset Sources
The S1C17624/604/622/602/621 has three initial reset sources that initialize the internal circuits.
(1) #RESET pin (external initial reset)
(2) Key-entry reset using the P0 ports (P00–P03 pins) (software selectable external initial reset)
(3) Watchdog timer (software selectable internal initial reset)
Figure 5.1.1 shows the configuration of the initial reset circuit.
#RESET
P00
P01
P02
P03
Watchdog
The CPU and peripheral circuits are initialized by the active signal from an initial reset source. When the reset sig-
nal is negated, the CPU starts reset handling. The reset handling reads the reset vector (reset handler start address)
from the beginning of the vector table and starts executing the program (initial routine) beginning with the read ad-
dress.
5.1.1 #ReSeT Pin
By setting the #RESET pin to low level, the S1C17624/604/622/602/621 enters initial reset state. In order to initial-
ize the S1C17624/604/622/602/621 for sure, the #RESET pin must be held at low for more than the prescribed time
(see "Input/Output Pin Characteristics" in the "Electrical Characteristics" chapter) after the power supply voltage is
supplied.
Initial reset state is canceled when the #RESET pin at low level is set to high level and the CPU starts executing the
reset interrupt handler.
The #RESET pin is a CMOS Schmitt level input port with a built-in pull-up resistor.
5.1.2 P0 Port Key-entry Reset
Entering low level simultaneously to the ports (P00–P03) selected with software triggers an initial reset. For details
of the key-entry reset function, see the "I/O Ports (P)" chapter.
note: The P0 port key-entry reset function cannot be used for power-on reset as it must be enabled with
software.
S1C17624/604/622/602/621 TeChniCal Manual
Reset input signal
Key-entry reset signal
P0 ports
WDT reset signal
timer
Figure 5. 1.1 Configuration of Initial Reset Circuit
Seiko epson Corporation
5 iniTial ReSeT
Internal reset signal
(to core and peripheral modules)
5-1