Epson S1C17624 Technical Manual page 326

aPPenDiX a liST OF i/O ReGiSTeRS
Peripheral address
16-bit PWM 0x5300
timer (T16E)
0x5302
Ch.0
0x5304
(16-bit device)
0x5306
0x5308
0x530a
0x530c
MISC registers 0x5320
(16-bit device)
0x5322
0x5324
0x5326
0x5328
0x532a
0x532c
IR remote 0x5340
controller
0x5342
(16-bit device)
0x5344
0x5346
A/D converter 0x5380
(16-bit device)
0x5382
0x5384
0x5386
R/F converter 0x53a0
(16-bit device)
0x53a2
0x53a4
0x53a6
0x53a8
0x53aa
0x53ac
0x53ae
16-bit PWM 0x5400
timer (T16A2)
0x5402
Ch.0
0x5404
(16-bit device)
0x5406
(S1C17624/604)
0x5408
0x540a
0x540c
16-bit PWM 0x5420
timer (T16A2)
0x5422
Ch.1
0x5424
(16-bit device)
0x5426
(S1C17624/604)
0x5428
0x542a
0x542c
Core i/O Reserved area (0xffff84–0xffffd0)
Peripheral address
S1C17 Core I/O 0xffff84
0xffff90
0xffffa0
0xffffb4
0xffffb8
0xffffbc
0xffffd0
note: Addresses marked as "Reserved" or unused peripheral circuit areas not marked in the table must
not be accessed by application programs.
aP-a-4
Register name
T16E_CA0 T16E Ch.0 Compare Data A Register
T16E_CB0 T16E Ch.0 Compare Data B Register
T16E_TC0 T16E Ch.0 Counter Data Register
T16E_CTL0 T16E Ch.0 Control Register
T16E_DF0 T16E Ch.0 Clock Division Ratio Select Register Selects the count clock.
T16E_IMSK0 T16E Ch.0 Interrupt Mask Register
T16E_IFLG0 T16E Ch.0 Interrupt Flag Register
MISC_FL FLASHC Control Register
MISC_OSC1 OSC1 Peripheral Control Register
MISC_PROT MISC Protect Register
MISC_IRAMSZ IRAM Size Select Register
MISC_TTBRL Vector Table Address Low Register
MISC_TTBRH Vector Table Address High Register
MISC_PSR PSR Register
REMC_CFG REMC Configuration Register
REMC_CAR REMC Carrier Length Setup Register
REMC_LCNT REMC Length Counter Register
REMC_INT REMC Interrupt Control Register
ADC10_ADD A/D Conversion Result Register
ADC10_TRG A/D Trigger/Channel Select Register
ADC10_CTL A/D Control/Status Register
ADC_DIV A/D Clock Control Register
RFC_CTL RFC Control Register
RFC_TRG RFC Oscillation Trigger Register
RFC_MCL RFC Measurement Counter Low Register
RFC_MCH RFC Measurement Counter High Register
RFC_TCL RFC Time Base Counter Low Register
RFC_TCH RFC Time Base Counter High Register
RFC_IMSK RFC Interrupt Mask Register
RFC_IFLG RFC Interrupt Flag Register
T16A_CTL0 T16A Counter Ch.0 Control Register
T16A_TC0 T16A Counter Ch.0 Data Register
T16A_CCCTL0 T16A Comparator/Capture Ch.0 Control
Register
T16A_CCA0 T16A Compare/Capture Ch.0 A Data Register Compare A/capture A data
T16A_CCB0 T16A Compare/Capture Ch.0 B Data Register Compare B/capture B data
T16A_IEN0 T16A Compare/Capture Ch.0 Interrupt Enable
Register
T16A_IFLG0 T16A Compare/Capture Ch.0 Interrupt Flag
Register
T16A_CTL1 T16A Counter Ch.1 Control Register
T16A_TC1 T16A Counter Ch.1 Data Register
T16A_CCCTL1 T16A Comparator/Capture Ch.1 Control
Register
T16A_CCA1 T16A Compare/Capture Ch.1 A Data Register Compare A/capture A data
T16A_CCB1 T16A Compare/Capture Ch.1 B Data Register Compare B/capture B data
T16A_IEN1 T16A Compare/Capture Ch.1 Interrupt Enable
Register
T16A_IFLG1 T16A Compare/Capture Ch.1 Interrupt Flag
Register
Register name
IDIR Processor ID Register
DBRAM Debug RAM Base Register
DCR Debug Control Register
IBAR1 Instruction Break Address Register 1
IBAR2 Instruction Break Address Register 2
IBAR3 Instruction Break Address Register 3
IBAR4 Instruction Break Address Register 4
Seiko epson Corporation
Function
Sets compare data A.
Sets compare data B.
Counter data
Sets the timer mode and starts/stops the timer.
Sets the interrupt mask.
Indicates and reset interrupt occurrence
status.
Sets FLASHC access condition.
Enables peripheral operations in debug mode
(except PCLK).
Enables writing to the MISC registers.
Selects the IRAM size.
Sets vector table address.
Indicates the S1C17 Core PSR values.
Controls the clock and data transfer.
Sets the carrier H/L section lengths.
Sets the transmit/receive data length.
Controls interrupts.
A/D converted data
Sets start/end channels and conversion mode.
Controls A/D converter and indicates conver-
sion status.
Controls A/D converter clock.
Controls R/F converter.
Controls oscillations.
Measurement counter data
Time base counter data
Enables/disables interrupts.
Indicates/resets interrupt occurrence status.
Controls the counter.
Counter data
Controls the comparator/capture block and
TOUT.
Enables/disables interrupts.
Displays/sets interrupt occurrence status.
Controls the counter.
Counter data
Controls the comparator/capture block and
TOUT.
Enables/disables interrupts.
Displays/sets interrupt occurrence status.
Function
Indicates the processor ID.
Indicates the debug RAM base address.
Controls debugging.
Sets Instruction break address #1.
Sets Instruction break address #2.
Sets Instruction break address #3.
Sets Instruction break address #4.
S1C17624/604/622/602/621 TeChniCal Manual