Epson S1C17624 Technical Manual page 290

To use this interrupt, set SVDIE/SVD_IMSK register to 1. When SVDIE is set to 0 (default), interrupt requests
for this cause will not be sent to the interrupt controller (ITC).
If SVDIF is set to 1 while SVDIE is set to 1 (interrupt enabled), the SVD module outputs an interrupt request to
the ITC. An interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied.
For more information on interrupt processing, see the "Interrupt Controller (ITC)" chapter.
notes: • To prevent interrupt recurrences, the SVD module interrupt flag SVDIF must be reset in the
interrupt handler routine after an SVD interrupt has occurred.
• To prevent unwanted interrupts, SVDIF should be reset before enabling SVD interrupts with
SVDIE.
26.6 Control Register Details
address
0x5066 OSC_SVD SVD Clock Control Register
0x5100 SVD_EN SVD Enable Register
0x5101 SVD_CMP SVD Comparison Voltage Register
0x5102 SVD_RSLT SVD Detection Result Register
0x5103 SVD_IMSK SVD Interrupt Mask Register
0x5104 SVD_IFLG SVD Interrupt Flag Register
The SVD module registers are described in detail below. These are 8-bit registers.
note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1.
SVD Clock Control Register (OSC_SVD)
Register name address Bit
SVD Clock 0x5066 D7–2 –
Control Register (8 bits) D1
(OSC_SVD)
D0
D[7:2] Reserved
D1 SVDSRC: SVD Clock Source Select Bit
Selects the clock source for the SVD circuit.
1 (R/W): OSC1 (default)
0 (R/W): HSCLK/512
When OSC1 is selected as the clock source, the OSC1 clock (typ. 32.768 kHz) is directly used as SVD-
CLK. When HSCLK is selected as the clock source, SVDCLK is generated by dividing HSCLK (IOSC
or OSC3 clock) by 512.
D0 SVDCKen: SVD Clock enable Bit
Enables or disables the operation clock supply to the SVD circuit.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
The SVDCKEN default setting is 0, which disables the clock supply. Setting SVDCKEN to 1 feeds the
clock selected to the SVD circuit.
SVD enable Register (SVD_en)
Register name address Bit
SVD enable 0x5100 D7–1 –
Register (8 bits)
D0
(SVD_en)
D[7:1] Reserved
S1C17624/604/622/602/621 TeChniCal Manual
Table 26. 6.1 List of SVD Registers
Register name
name Function
reserved
SVDSRC
SVD clock source select
SVDCKen
SVD clock enable
name Function
reserved
SVDen SVD enable
Seiko epson Corporation
26 SuPPlY VOlTaGe DeTeCTOR (SVD)
Function
Selects the operating clock.
Enables/disables the SVD operation.
Sets the comparison voltage.
Voltage detection results
Enables/disables interrupts.
Indicates/resets interrupt occurrence status.
Setting
–
1 OSC1 0 HSCLK/512
1 Enable 0 Disable
Setting
–
1 Enable 0 Disable
init. R/W Remarks
– – 0 when being read.
1 R/W
0 R/W
init. R/W Remarks
– – 0 when being read.
0 R/W
26-3