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aPPenDiX a liST OF i/O ReGiSTeRS
Register name address
Bit
interrupt level
0x4312
D15–11 –
Setup Register 6
(16 bits)
D10–8 ilV13[2:0]
(iTC_lV6)
D7–3 –
D2–0 ilV12[2:0]
interrupt level
0x4314
D15–11 –
Setup Register 7
(16 bits)
D10–8 ilV15[2:0]
(iTC_lV7)
D7–3 –
D2–0 ilV14[2:0]
interrupt level
0x4316
D15–11 –
Setup Register 8
(16 bits)
D10–8 ilV17[2:0]
(iTC_lV8)
D7–3 –
D2–0 ilV16[2:0]
interrupt level
0x4318
D15–11 –
Setup Register 9
(16 bits)
D10–8 ilV19[2:0]
(iTC_lV9)
D7–3 –
D2–0 ilV18[2:0]
0x4320–0x4326
Register name address
Bit
SPi Ch.0
0x4320
D15–3 –
Status Register
(16 bits)
D2
(SPi_ST0)
D1
D0
SPi Ch.0
0x4322
D15–8 –
Transmit Data
(16 bits)
D7–0 SPTDB[7:0] SPI transmit data buffer
Register
(SPi_TXD0)
SPi Ch.0
0x4324
D15–8 –
Receive Data
(16 bits)
D7–0 SPRDB[7:0] SPI receive data buffer
Register
(SPi_RXD0)
SPi Ch.0
0x4326
D15–10 –
Control Register
(16 bits)
D9
(SPi_CTl0)
D8
D7–6 –
D5
D4
D3
D2
D1
D0
0x4340–0x4346
Register name address
Bit
i
2
C Master
0x4340
D15–1 –
enable Register
(16 bits)
(i2CM_en)
D0
i
2
C Master
0x4342
D15–10 –
Control Register
(16 bits)
D9
(i2CM_CTl)
D8
D7–5 –
D4
D3–2 –
D1
D0
i
2
C Master
0x4344
D15–12 –
Data Register
(16 bits)
D11
(i2CM_DaT)
D10
D9
D8
D7–0 RTDT[7:0]
i
2
C Master
0x4346
D15–2 –
interrupt
(16 bits)
D1
Control Register
D0
(i2CM_iCTl)
aP-a-10
name
Function
reserved
I2CS/UART Ch.1 interrupt level
reserved
UART Ch.0 interrupt level
reserved
I2CM interrupt level
reserved
SPI Ch.0 interrupt level
reserved
T16A2 Ch.1 interrupt level
reserved
REMC interrupt level
reserved
RFC interrupt level
reserved
ADC10 interrupt level
name
Function
reserved
SPBSY
Transfer busy flag (master)
ss signal low flag (slave)
SPRBF
Receive data buffer full flag
SPTBe
Transmit data buffer empty flag
reserved
SPTDB7 = MSB
SPTDB0 = LSB
reserved
SPRDB7 = MSB
SPRDB0 = LSB
reserved
MClK
SPI clock source select
MlSB
LSB/MSB first mode select
reserved
SPRie
Receive data buffer full int. enable 1 Enable
SPTie
Transmit data buffer empty int. enable 1 Enable
CPha
Clock phase select
CPOl
Clock polarity select
MSSl
Master/slave mode select
SPen
SPI enable
name
Function
reserved
i2CMen
I
2
C master enable
reserved
RBuSY
Receive busy flag
TBuSY
Transmit busy flag
reserved
nSeRM
Noise remove on/off
reserved
STP
Stop control
STRT
Start control
reserved
RBRDY
Receive buffer ready flag
RXe
Receive execution
TXe
Transmit execution
RTaCK
Receive/transmit ACK
Receive/transmit data
RTDT7 = MSB
RTDT0 = LSB
reserved
RinTe
Receive interrupt enable
TinTe
Transmit interrupt enable
Seiko epson Corporation
Setting
init. R/W
–
0 to 7
0x0 R/W
–
0 to 7
0x0 R/W
–
0 to 7
0x0 R/W
–
0 to 7
0x0 R/W
–
0 to 7
0x0 R/W
–
0 to 7
0x0 R/W
–
0 to 7
0x0 R/W
–
0 to 7
0x0 R/W
Setting
init. R/W
–
1 Busy
0 Idle
1 ss = L
0 ss = H
1 Full
0 Not full
1 Empty
0 Not empty
–
0x0 to 0xff
0x0 R/W
–
0x0 to 0xff
0x0
–
1 T16 Ch.1
0 PCLK/4
1 LSB
0 MSB
–
0 Disable
0 Disable
1 Data out
0 Data in
1 Active L
0 Active H
1 Master
0 Slave
1 Enable
0 Disable
Setting
init. R/W
–
1 Enable
0 Disable
–
1 Busy
0 Idle
1 Busy
0 Idle
–
1 On
0 Off
–
1 Stop
0 Ignored
1 Start
0 Ignored
–
1 Ready
0 Empty
1 Receive
0 Ignored
1 Transmit
0 Ignored
1 Error
0 ACK
0x0 to 0xff
0x0 R/W
–
1 Enable
0 Disable
1 Enable
0 Disable
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
–
–
0 when being read.
–
–
0 when being read.
–
–
0 when being read.
–
–
0 when being read.
–
–
0 when being read.
–
–
0 when being read.
–
–
0 when being read.
–
–
0 when being read.
SPi Ch.0
Remarks
–
–
0 when being read.
0
R
0
R
1
R
–
–
0 when being read.
–
–
0 when being read.
R
–
–
0 when being read.
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
0
R/W These bits must be
0
R/W
set before setting
SPEN to 1.
0
R/W
0
R/W
i
2
C Master
Remarks
–
–
0 when being read.
0
R/W
–
–
0 when being read.
0
R
0
R
–
–
0 when being read.
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
–
–
0 when being read.
0
R
0
R/W
0
R/W
0
R/W
–
–
0 when being read.
0
R/W
0
R/W
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