Table of Contents
Advertisement
notes: • The clock generator (CLG) must be configured to supply PCLK to the peripheral modules be-
fore running the timer.
• Make sure the counter is halted before setting the count clock.
For detailed information on the CLG control, see the "Clock Generator (CLG)" chapter.
11.3.2
external Clock Mode
External clock mode uses the clock and pulses input via the I/O port as the count clock. This enables T16 to be used
as an event counter. Timer operations other than the input clock are the same as for internal clock mode.
external clock input port
To input an external clock to T16, the I/O port shared with an EXCLx input must be set to input mode in advance.
For detailed information on the port control, see the "I/O Ports (P)" chapter.
Signal polarity selection
CKACTV/T16_CTLx register is used in external clock mode to select either the falling edge or rising edge of
the input signal for counting.
Counting down uses the rising edge when CKACTV is 1 (default) and uses the falling edge when set to 0.
External input clock
PRUN
Counter (CKACTV = 1)
Counter (CKACTV = 0)
11.3.3
Pulse Width Measurement Mode
In pulse width measurement mode, when pulses with the specified polarity are input from the external clock port,
the internal clock is fed only while the input pulse is active, enabling counting. This enables T16 to generate an in-
terrupt when a pulse with the specified width or greater, or to measure the input pulse width.
Pulse input port
The I/O port (EXCLx) used for external pulse input is the same as for external clock mode.
Input pulses by enabling the EXCLx port function corresponding to the timer channel to be used.
Count clock selection
Counting uses the divided PCLK clock selected by DF[3:0]/T16_CLKx register in the same way as for internal
clock mode. Select the clock to suit approximate input pulse widths and counting accuracy (see Table 11.3.1.1).
Signal polarity selection
CKACTV/T16_CTLx register is used to select the active level for the pulses counted. Setting CKACTV to 1
(default) will measure the high period and setting it to 0 will measure the low period.
S1C17624/604/622/602/621 TeChniCal Manual
n
n-1
n-2
n-3
n
n-1
n-2
Figure 11.
3.2.1 Counting in External Clock Mode
Seiko epson Corporation
n-4
n-5
n-6
n-7
n-8
n-3
n-4
n-5
n-6
n-7
11 16-BiT TiMeRS (T16)
n-9 n-10
n-8
n-9 n-10
11-3
Advertisement
Table of Contents
