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14 8-BiT OSC1 TiMeR (T8OSC1)
D0
T8OiF: T8OSC1 interrupt Flag Bit
Indicates whether the cause of compare match interrupt has occurred or not.
1 (R):
Cause of interrupt has occurred
0 (R):
No cause of interrupt has occurred (default)
1 (W):
Flag is reset
0 (W):
Ignored
T8OIF is the T8OSC1 module interrupt flag. Setting T8OIE/T8OSC1_IMSK register to 1 sets this
to 1 when the counter matches the compare data register value during counting. At the same time the
T8OSC1 interrupt request signal is output to the ITC and an interrupt occurs if the ITC and S1C17 Core
interrupt conditions are met.
T8OIF is reset by writing 1.
notes: • To prevent interrupt recurrences, the T8OSC1 module interrupt flag T8OIF must be reset in
the interrupt handler routine following a T8OSC1 interrupt.
• To prevent generating unnecessary interrupts, reset T8OIF before enabling compare match
interrupts using T8OIE.
T8OSC1 PWM Duty Data Register (T8OSC1_DuTY)
Register name address
Bit
T8OSC1 PWM
0x50c5
D7–0 T8ODTY[7:0] PWM output duty data
Duty Data
(8 bits)
Register
(T8OSC1_DuTY)
D[7:0]
T8ODTY[7:0]: PWM Output Duty Data Bits
Sets the data that determines the duty ratio of PWM waveform. (Default: 0x0)
The set data is compared against the counter data. If the contents match, the timer output waveform
rises. If the counter data matches the compare data, the timer output waveform falls. These processes do
not affect the counter data or count process.
14-8
name
Function
T8ODTY7 = MSB
T8ODTY0 = LSB
Seiko epson Corporation
Setting
init. R/W
0x0 to 0xff
0x0 R/W
S1C17624/604/622/602/621 TeChniCal Manual
Remarks
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