Epson S1C17624 Technical Manual page 228

i 2 C Slave address Setup Register (i2CS_SaDRS)
Register name address Bit
i 2 C Slave 0x4364 D15–7 –
address Setup D6–0 SaDRS[6:0] I
(16 bits)
Register
(i2CS_SaDRS)
D[15:7] Reserved
D[6:0] SaDRS[6:0]: i2CS address Bits
Sets the slave address of the I2CS module to this register. (Default: 0x0)
i 2 C Slave Control Register (i2CS_CTl)
Register name address Bit
2
i C Slave 0x4366 D15–9 –
Control Register
(16 bits)
D8
(i2CS_CTl)
D7
D6
D5
D4
D3
D2
D1
D0
D[15:9] Reserved
D8 TBuF_ClR: i2CS_TRnS Register Clear Bit
Clears the I2CS_TRNS register.
1 (R/W): Clear state
0 (R/W): Normal state (clear state cancellation) (default)
When TBUF_CLR is set to 1, the I2CS_TRNS register enters clear state. After that writing 0 to TBUF_
CLR returns the I2CS_TRNS register to normal state. It is not necessary to insert a waiting time be-
tween writing 1 and 0.
If a new transmission is started when the I2CS_TRNS register still stores data for the previous trans-
mission that has already finished, the data will be sent when TXEMP/I2CS_ASTAT register is set. In
order to avoid this problem, clear the I2CS_TRNS register using TBUF_CLR before starting transmis-
sion (before slave selection). The clear operation is not required if transmit data is written to the I2CS_
TRNS register before TXEMP is set to 1.
Data can be written to the I2CS_TRNS register even if it is placed into clear state (TBUF_CLR = 1).
However, this writing does not reset TXEMP to 0. Note that TXEMP is not reset to 0 when TBUF_CLR
is set back to 0. Therefore, data must be written to the I2CS_TRNS register when TBUF_CLR = 0.
D7 i2CSen: i 2 C Slave enable Bit
Enables or disables operations of the I2CS module.
1 (R/W): Enabled
0 (R/W): Disabled (default)
When I2CSEN is set to 1, the I2CS module is activated and data transfer is enabled.
When I2CSEN is set to 0, the I2CS module goes off.
D6 SOFTReSeT: Software Reset Bit
Resets the I2CS module.
1 (R/W): Reset
0 (R/W): Cancel reset state (default)
To reset the I2CS module, write 1 to SOFTRESET to place the I2CS module into reset status, then
write 0 to SOFTRESET to release it from reset status. It is not necessary to insert a waiting time be-
tween writing 1 and 0. The I2CS module initializes the I
and SCL1 pins into high-impedance to be ready to detect a start condition. Furthermore, the I2CS con-
trol bits except for SOFTRESET are initialized. Perform the software reset in the initial setting process
before staring communication.
S1C17624/604/622/602/621 TeChniCal Manual
name Function
reserved
2 C slave address
name Function
reserved
TBuF_ClR I2CS_TRNS register clear
i2CSen
I 2 C slave enable
SOFTReSeT Software reset
naK_anS
NAK answer
BFReQ_en Bus free request enable
ClKSTR_en Clock stretch On/Off
nF_en
Noise filter On/Off
aSDeT_en Async.address detection On/Off
COM_MODe I
2 C slave communication mode
Seiko epson Corporation
Setting init. R/W
–
0–0x7f 0x0 R/W
Setting init. R/W
–
1 Clear state 0 Normal
1 Enable 0 Disable
1 Reset 0 Cancel
1 NAK 0 ACK
1 Enable 0 Disable
1 On 0 Off
1 On 0 Off
1 On 0 Off
1 Active 0 Standby
2 C communication process and put the SDA1
2
21 i C SlaVe (i2CS)
Remarks
– – 0 when being read.
Remarks
– – 0 when being read.
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
21-11