Epson S1C17624 Technical Manual page 301

Mode setting
instruction
value
0x04 ld.ca %rd,%rs
or 0x05
(ext
imm9)
ld.ca %rd,imm7
0x14
ld.ca %rd,%rs
or 0x15
(ext
imm9)
ld.ca %rd,imm7
Example:
ld.cw %r0,0x4
ld.ca %r0,%r1
ld.cw %r0,0x13 ; Sets the modes (operation result read mode and 16 high-order bits output mode).
ld.ca %r1,%r0
28.4 Division
The division function performs "B (16 bits) ÷ C (16 bits) = A (16 bits), residue D (16 bits)."
To perform a division, set the operation mode to 0x8 (unsigned division) or 0x9 (signed division). Then send the
16-bit dividend (B) and 16-bit divisor (C) to the multiplier/divider using a "ld.ca" instruction. The quotient and
the residue will be stored in the low-order 16 bits and the high-order 16 bits of the operation result register, respec-
tively. The 16-bit quotient or residue according to the output mode specification and the flag status will be returned
to the CPU registers. Another 16-bit result should be read by setting the multiplier/divider into operation result read
mode.
Mode setting
instruction
value
0x08
ld.ca %rd,%rs
or 0x09
(ext
imm9)
ld.ca %rd,imm7
0x018 ld.ca %rd,%rs
or 0x19
(ext
imm9)
ld.ca %rd,imm7
S1C17624/604/622/602/621 TeChniCal Manual
Table 28. 3.1 Operation in Multiplication Mode
Operations
res[31:0] ← %rd × %rs
%rd ← res[15:0]
res[31:0] ← %rd × imm7/16
%rd ← res[15:0]
res[31:0] ← %rd × %rs
%rd ← res[31:16]
res[31:0] ← %rd × imm7/16
%rd ← res[31:16]
; Sets the modes (unsigned multiplication mode and 16 low-order bits output mode).
; Performs "res = %r0 × %r1" and loads the 16 low-order bits of the result to %r0.
; Loads the 16 high-order bits of the result to %r1.
Argument 2
Argument 1
S1C17 Core
Coprocessor
output (16 bits)
Flag output
Figure 28. 4.1 Data Path in Division Mode
Table 28. 4.1 Operation in Division Mode
Operations
res[31:0] ← %rd ÷ %rs
%rd ← res[15:0] (quotient)
res[31:0] ← %rd ÷ imm7/16
%rd ← res[15:0] (quotient)
res[31:0] ← %rd ÷ %rs
%rd ← res[31:16] (residue)
res[31:0] ← %rd ÷ imm7/16
%rd ← res[31:16] (residue)
Seiko epson Corporation
28 MulTiPlieR/DiViDeR (COPRO)
Flags
psr (CVZN) ← 0b0000 The operation result register
16 bits
÷
16 bits
Operation
result
Operation result
register
Selector
Flags
psr (CVZN) ← 0b0000 The operation result register
Remarks
keeps the operation result until
it is rewritten by other opera-
tion.
res: operation result register
Remarks
keeps the operation result until
it is rewritten by other opera-
tion.
res: operation result register
28-3